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EP2704151
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EP About this file: EP2704151
| EP2704151 - Semiconductor device and memory test method [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 18.12.2015 Database last updated on 25.09.2024 | Most recent event Tooltip | 18.12.2015 | Application deemed to be withdrawn | published on 20.01.2016 [2016/03] | Applicant(s) | For all designated states FUJITSU LIMITED 1-1, Kamikodanaka 4-chome, Nakahara-ku Kawasaki-shi Kanagawa 211-8588 / JP | For all designated states Socionext Inc. 2-10-23 Shin-Yokohama, Kohoku-ku Yokohama-shi, Kanagawa 222-0033 / JP | [2015/24] |
| Former [2014/10] | For all designated states FUJITSU LIMITED 1-1, Kamikodanaka 4-chome, Nakahara-ku Kawasaki-shi Kanagawa 211-8588 / JP | ||
| For all designated states Fujitsu Semiconductor Limited 2-10-23 Shin-Yokohama Kohoku-ku, Yokohama-shi Kanagawa 222-0033 / JP | Inventor(s) | 01 /
Yamanaka, Hitoshi c/o FUJITSU LIMITED 1-1, Kamikodanaka 4-chome Nakahara-ku Kawasaki-shi Kanagawa 211-8588 / JP | 02 /
Gomi, Kenichi c/o FUJITSU SEMICONDUCTOR LIMITED 2-10-23 Shin-Yokohama Kohoku-ku Yokohama-shi Kanagawa 222-0033 / JP | [2014/10] | Representative(s) | Hoffmann Eitle Patent- und Rechtsanwälte PartmbB Arabellastrasse 30 81925 München / DE | [N/P] |
| Former [2014/10] | HOFFMANN EITLE Patent- und Rechtsanwälte Arabellastrasse 4 81925 München / DE | Application number, filing date | 13178173.4 | 26.07.2013 | [2014/10] | Priority number, date | JP20120192638 | 31.08.2012 Original published format: JP 2012192638 | [2014/10] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP2704151 | Date: | 05.03.2014 | Language: | EN | [2014/10] | Type: | A3 Search report | No.: | EP2704151 | Date: | 07.01.2015 | Language: | EN | [2015/02] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 09.12.2014 | Classification | IPC: | G11C29/32 | [2015/02] | CPC: |
G11C29/32 (EP,US);
G06F12/0864 (US);
G11C2029/0401 (EP,US);
G11C2029/0405 (EP,US)
|
| Former IPC [2014/10] | G11C29/26, G11C29/30 | Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2014/10] | Extension states | BA | Not yet paid | ME | Not yet paid | Title | German: | Halbleitervorrichtung und Speicherprüfverfahren | [2014/10] | English: | Semiconductor device and memory test method | [2014/10] | French: | Dispositif semi-conducteur et procédé d'essai de mémoire | [2014/10] | Examination procedure | 08.07.2015 | Application deemed to be withdrawn, date of legal effect [2016/03] | 31.08.2015 | Despatch of communication that the application is deemed to be withdrawn, reason: examination fee not paid in time [2016/03] | Fees paid | Penalty fee | Additional fee for renewal fee | 31.07.2015 | 03 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US5701431 (WHITTAKER BRUCE ERNEST [US]) [A] 1,5 * page 1, column 1, line 58 - column 2, line 6; figure 1 *; | [I]US2004073841 (TOROS ZEYNEP M [US], et al) [I] 1-6 * paragraphs [0039] - [0041] - [0074] , [0011]; figure 2; claim 1 *; | [AD]US2009245001 (HIRAIDE TAKAHISA [JP]) [AD] 1-6* the whole document *; | [I]US7707472 (DASTIDAR JAYABRATA GHOSH [US]) [I] 1,5 * figure 2 * | by applicant | JP2010040085 |