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Extract from the Register of European Patents

EP About this file: EP2923381

EP2923381 - DEVICE ARCHITECTURE AND METHOD FOR IMPROVED PACKING OF VERTICAL FIELD EFFECT DEVICES [Right-click to bookmark this link]
StatusThe application has been withdrawn
Status updated on  06.12.2019
Database last updated on 24.08.2024
FormerExamination is in progress
Status updated on  07.08.2019
Most recent event   Tooltip06.12.2019Withdrawal of applicationpublished on 08.01.2020  [2020/02]
Applicant(s)For all designated states
D3 Semiconductor LLC
15050 E. Beltwood Parkway
Addison, TX 75001 / US
[2015/40]
Inventor(s)01 / HARRINGTON, Thomas, E.
15050 E. Beltwood Parkway
Addison, TX 75001 / US
02 / YANG, Robert, Kuo-chang
15050 E. Beltwood Parkway
Addison, TX 75001 / US
 [2015/40]
Representative(s)Barton, Matthew Thomas
Forresters IP LLP
Skygarden
Erika-Mann-Strasse 11
80636 München / DE
[N/P]
Former [2015/40]Barton, Matthew Thomas
Forresters
Skygarden
Erika-Mann-Strasse 11
80636 München / DE
Application number, filing date13857471.026.11.2013
[2015/40]
WO2013US72095
Priority number, dateUS201261729686P26.11.2012         Original published format: US 201261729686 P
[2015/40]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO2014082095
Date:30.05.2014
Language:EN
[2014/22]
Type: A1 Application with search report 
No.:EP2923381
Date:30.09.2015
Language:EN
The application published by WIPO in one of the EPO official languages on 30.05.2014 takes the place of the publication of the European patent application.
[2015/40]
Search report(s)International search report - published on:US30.05.2014
(Supplementary) European search report - dispatched on:EP18.07.2016
ClassificationIPC:H01L29/04, H01L29/78, H01L21/336
[2016/33]
CPC:
H01L29/7813 (EP,US); H01L21/26586 (US); H01L21/3083 (US);
H01L21/31155 (US); H01L29/045 (EP,US); H01L29/0634 (EP,US);
H01L29/0653 (EP,US); H01L29/0696 (EP,US); H01L29/1095 (EP,US);
H01L29/4236 (US); H01L29/42376 (US); H01L29/4238 (EP,US);
H01L29/66348 (EP,US); H01L29/66666 (US); H01L29/66719 (US);
H01L29/66734 (EP,US); H01L29/7397 (EP,US); H01L29/7827 (US) (-)
Former IPC [2015/40]H01L29/04
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2015/40]
TitleGerman:VORRICHTUNGSARCHITEKTUR UND VERFAHREN FÜR EIN VERBESSERTES GEHÄUSE VON VERTIKALEN FELDEFFEKTANORDNUNGEN[2015/40]
English:DEVICE ARCHITECTURE AND METHOD FOR IMPROVED PACKING OF VERTICAL FIELD EFFECT DEVICES[2015/40]
French:ARCHITECTURE DE DISPOSITIF ET PROCÉDÉ D'EMBALLAGE AMÉLIORÉ DE DISPOSITIFS À EFFET DE CHAMP VERTICAUX[2015/40]
Entry into regional phase26.06.2015National basic fee paid 
26.06.2015Search fee paid 
26.06.2015Designation fee(s) paid 
26.06.2015Examination fee paid 
Examination procedure26.06.2015Examination requested  [2015/40]
14.02.2017Amendment by applicant (claims and/or description)
12.08.2019Despatch of a communication from the examining division (Time limit: M04)
05.12.2019Application withdrawn by applicant  [2020/02]
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  12.08.2019
Fees paidRenewal fee
25.11.2015Renewal fee patent year 03
30.11.2016Renewal fee patent year 04
30.11.2017Renewal fee patent year 05
30.11.2018Renewal fee patent year 06
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Documents cited:Search[XA]WO2012149195  (FAIRCHILD SEMICONDUCTOR [US], et al) [X] 1-4,7-9,12,13,15 * paragraph [000111] - paragraph [000116]; figures 19A-19L * * paragraph [00143] - paragraph [00145]; figures 27A,27B,28 * [A] 11;
 [Y]US2004036121  (AOKI TAKAAKI [JP], et al) [Y] 1-10,12-15 * paragraph [0059] - paragraph [0062]; figure 2 * * paragraph [0128] - paragraph [0132]; figure 11 *;
 [Y]US2007029597  (LEE JAE-GIL [KR], et al) [Y] 1-10,12-15 * paragraph [0003] - paragraph [0004] * * paragraph [0058] - paragraph [0061]; figures 6,7 * * paragraph [0078] - paragraph [0080]; figure 11 *;
 [Y]WO2011013379  (FUJI ELECTRIC SYSTEMS CO LTD [JP], et al) [Y] 1-10,12-15 * paragraph [0077] - paragraph [0083]; figures 1-4 * * paragraph [0121]; figures 50-51 *;
 [Y]JP2005317828  (SUMITOMO ELECTRIC INDUSTRIES) [Y] 5 * abstract * * paragraph [0055] *;
 [A]  - E.A. Lewis, "The Effect of Surface Orientation on Silicon Oxidation Kinetics", J. Electrochem. Soc: SOLID-STATE SCIENCE AND TECHNOLOGY, (19870901), pages 2322 - 2329, URL: http://jes.ecsdl.org/content/134/9/2332.full.pdf, (20160707), XP055286806 [A] 10,14 * the whole document *

DOI:   http://dx.doi.org/10.1149/1.2100881
International search[Y]US2005035401  (YAMAGUCHI HITOSHI [JP], et al);
 [Y]US2007108512  (SEDLMAIER STEFAN [DE], et al);
 [Y]WO2012149195  (FAIRCHILD SEMICONDUCTOR [US], et al);
 [Y]US2008258239  (ISHIGURO TAKESHI [JP]);
 [Y]US2011180812  (MASUDA TAKEYOSHI [JP], et al);
 [Y]US2004036121  (AOKI TAKAAKI [JP], et al);
 [A]US2010193800  (UCHIDA MASAO [JP], et al);
 [A]US2006102953  (MIURA YOSHINAO [JP], et al)
by applicantWO2012149195
 US2004036121
 US2007029597
 WO2011013379
 JP2005317828
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.