EP2977989 - Sample-and-hold circuit for an interleaved analog-to-digital converter [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 13.03.2020 Database last updated on 19.10.2024 | |
Former | The patent has been granted Status updated on 05.04.2019 | ||
Former | Grant of patent is intended Status updated on 29.03.2019 | ||
Former | Request for examination was made Status updated on 19.02.2019 | ||
Former | Grant of patent is intended Status updated on 16.10.2018 | ||
Former | Request for examination was made Status updated on 26.09.2018 | ||
Former | Grant of patent is intended Status updated on 13.09.2018 | ||
Former | Request for examination was made Status updated on 29.08.2018 | Most recent event Tooltip | 01.07.2022 | Lapse of the patent in a contracting state New state(s): MK | published on 03.08.2022 [2022/31] | Applicant(s) | For all designated states IMEC VZW Kapeldreef 75 3001 Leuven / BE | [2019/19] |
Former [2016/04] | For all designated states IMEC VZW Kapeldreef 75 3001 Leuven / BE | Inventor(s) | 01 /
Verbruggen, Bob IMEC VZW Patent Department Kapeldreef 75 3001 Leuven / BE | 02 /
Deguchi, Kazuaki IMEC VZW Patent Department Kapeldreef 75 3001 Leuven / BE | 03 /
Craninckx, Jan IMEC VZW Patent Department Kapeldreef 75 3001 Leuven / BE | [2016/04] | Representative(s) | Patent Department IMEC IMEC vzw Patent Department Kapeldreef 75 3001 Leuven / BE | [2019/19] |
Former [2016/04] | DenK iP Hundelgemsesteenweg 1114 9820 Merelbeke / BE | Application number, filing date | 14178665.7 | 25.07.2014 | [2016/04] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP2977989 | Date: | 27.01.2016 | Language: | EN | [2016/04] | Type: | B1 Patent specification | No.: | EP2977989 | Date: | 08.05.2019 | Language: | EN | [2019/19] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 06.02.2015 | Classification | IPC: | G11C27/02, H03M1/12 | [2018/34] | CPC: |
G11C27/02 (EP,US);
H03M1/1245 (US)
|
Former IPC [2016/04] | G11C27/02 | Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2016/34] |
Former [2016/04] | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR | Title | German: | Abtast- und Halteschaltung für einen verschachtelten Analog-Digital-Wandler | [2016/04] | English: | Sample-and-hold circuit for an interleaved analog-to-digital converter | [2016/04] | French: | Circuit échantillonneur-bloqueur pour un convertisseur analogique-numérique entrelacé | [2016/04] | Examination procedure | 18.07.2016 | Amendment by applicant (claims and/or description) | 18.07.2016 | Examination requested [2016/34] | 14.09.2018 | Communication of intention to grant the patent | 17.09.2018 | Disapproval of the communication of intention to grant the patent by the applicant or resumption of examination proceedings by the EPO | 17.10.2018 | Communication of intention to grant the patent | 15.02.2019 | Disapproval of the communication of intention to grant the patent by the applicant or resumption of examination proceedings by the EPO | 15.02.2019 | Fee for grant paid | 15.02.2019 | Fee for publishing/printing paid | 28.03.2019 | Information about intention to grant a patent | 28.03.2019 | Receipt of the translation of the claim(s) | Opposition(s) | 11.02.2020 | No opposition filed within time limit [2020/16] | Fees paid | Renewal fee | 22.07.2016 | Renewal fee patent year 03 | 21.07.2017 | Renewal fee patent year 04 | 24.07.2018 | Renewal fee patent year 05 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | HU | 25.07.2014 | AL | 08.05.2019 | AT | 08.05.2019 | CY | 08.05.2019 | CZ | 08.05.2019 | DK | 08.05.2019 | EE | 08.05.2019 | ES | 08.05.2019 | FI | 08.05.2019 | HR | 08.05.2019 | IT | 08.05.2019 | LT | 08.05.2019 | LV | 08.05.2019 | MC | 08.05.2019 | MK | 08.05.2019 | MT | 08.05.2019 | NL | 08.05.2019 | PL | 08.05.2019 | RO | 08.05.2019 | RS | 08.05.2019 | SE | 08.05.2019 | SI | 08.05.2019 | SK | 08.05.2019 | SM | 08.05.2019 | TR | 08.05.2019 | IE | 25.07.2019 | LU | 25.07.2019 | BE | 31.07.2019 | CH | 31.07.2019 | LI | 31.07.2019 | BG | 08.08.2019 | NO | 08.08.2019 | GR | 09.08.2019 | IS | 08.09.2019 | PT | 08.09.2019 | [2022/31] |
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NO | 08.08.2019 | Documents cited: | Search | [A]US2006186948 (KELLY DANIEL F [US], et al) [A] 1-10 * paragraph [0050] - paragraph [0052]; figures 11-13 *; | [A]US2009039924 (ZANCHI ALFIO [US], et al) [A] 1-10* the whole document *; | [YDA]US8248282 (PAYNE ROBERT F [US], et al) [YD] 1-4,10 * column 6, line 35 - line 52; figure 5; claim 8 * [A] 5-9; | [YDA]US2013141261 (JOHANCSIK TRACY [US], et al) [YD] 1-4,10 * paragraph [0032] - paragraph [0044]; figures 4-6 * [A] 5-9 | by applicant | US8248282 | US2013141261 | - A.M. ABO ET AL., "A 1.5-V, 10-bit, 14.3-MSIs CMOS Pipeline Analog-to-Digital Converter", JSSC, (199905), vol. 34, no. 5 | - R.PAYNE ET AL., "A 12b 1GSIs SiGe BiCMOS Two-Way Time-Interleaved Pipeline ADC", ISSCC, (2011), pages 182 - 184 |