EP3155658 - MEMORY DIE WITH DIRECT INTEGRATION TO LOGIC DIE AND METHOD OF MANUFACTURING THE SAME [Right-click to bookmark this link] | |||
Former [2017/16] | METHOD FOR DIRECT INTEGRATION OF MEMORY DIE TO LOGIC DIE WITHOUT USE OF THROUGH SILICON VIAS (TSV) | ||
[2022/19] | Status | No opposition filed within time limit Status updated on 29.12.2023 Database last updated on 22.08.2024 | |
Former | The patent has been granted Status updated on 20.01.2023 | ||
Former | Grant of patent is intended Status updated on 26.08.2022 | ||
Former | Examination is in progress Status updated on 05.08.2022 | ||
Former | Grant of patent is intended Status updated on 01.05.2022 | ||
Former | Examination is in progress Status updated on 03.07.2020 | ||
Former | Request for examination was made Status updated on 20.03.2017 | ||
Former | The international publication has been made Status updated on 04.11.2016 | Most recent event Tooltip | 24.05.2024 | Lapse of the patent in a contracting state New state(s): IT | published on 26.06.2024 [2024/26] | Applicant(s) | For all designated states Intel Corporation 2200 Mission College Boulevard MS: RNB-4-150 Santa Clara, California 95052 / US | [2017/16] | Inventor(s) | 01 /
NELSON, Donald W. 16985 SW Blackberry Lane Beaverton, Oregon 97007 / US | 02 /
WEBB, M Clair 20180 SW Inglis Drive Aloha, Oregon 97007 / US | 03 /
MORROW, Patrick 6158 NW Landing Drive Portland, Oregon 97229 / US | 04 /
JUN, Kimin 1879 NW 193rd Avenue Unit 203 Hillsboro, Oregon 97006 / US | [2017/16] | Representative(s) | Goddar, Heinz J. Boehmert & Boehmert Anwaltspartnerschaft mbB Pettenkoferstrasse 22 80336 München / DE | [2023/08] |
Former [2017/16] | Goddar, Heinz J. BOEHMERT & BOEHMERT Anwaltspartnerschaft mbB Pettenkoferstrasse 20-22 80336 München / DE | Application number, filing date | 14895276.5 | 16.06.2014 | [2017/16] | WO2014US42574 | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO2015195082 | Date: | 23.12.2015 | Language: | EN | [2015/51] | Type: | A1 Application with search report | No.: | EP3155658 | Date: | 19.04.2017 | Language: | EN | The application published by WIPO in one of the EPO official languages on 23.12.2015 takes the place of the publication of the European patent application. | [2017/16] | Type: | B1 Patent specification | No.: | EP3155658 | Date: | 22.02.2023 | Language: | EN | [2023/08] | Search report(s) | International search report - published on: | KR | 23.12.2015 | (Supplementary) European search report - dispatched on: | EP | 26.01.2018 | Classification | IPC: | H01L25/16, H01L27/06, H01L23/12, H01L21/336, H01L29/78, H01L21/98, H01L23/538, H01L25/00, // H01L23/00, H01L25/18 | [2022/19] | CPC: |
H01L25/18 (EP);
H01L23/5389 (EP,KR,US);
H01L25/0652 (KR,US);
H01L23/5383 (EP,KR,US);
H01L23/5384 (US);
H01L24/03 (US);
H01L24/06 (US);
H01L24/17 (EP,US);
H01L24/27 (KR);
H01L25/0655 (US);
H01L25/50 (EP,US);
H01L2224/16145 (EP,US);
H01L2224/16225 (EP,KR,US);
H01L2224/16227 (EP,US);
H01L2224/17181 (EP,US);
H01L2224/81193 (EP,US);
H01L2224/81201 (EP,US);
H01L2224/81895 (EP,US);
H01L2224/81986 (EP,US);
H01L2224/9202 (EP,US);
H01L24/16 (EP,US);
H01L24/81 (EP,US);
H01L25/0657 (EP);
H01L2924/0002 (EP,US);
| C-Set: |
H01L2224/81201, H01L2924/00014 (US,EP);
H01L2224/81895, H01L2924/00014 (US,EP);
H01L2224/9202, H01L2224/11 (US,EP);
H01L2924/0002, H01L2924/00 (US); |
Former IPC [2018/09] | H01L27/06, H01L23/12, H01L21/60 | ||
Former IPC [2017/16] | H01L23/12, H01L21/60 | Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2017/16] | Extension states | BA | Not yet paid | ME | Not yet paid | Title | German: | SPEICHERCHIP MIT DIREKTER INTEGRATION MIT EINEM LOGIKCHIP UND VERFAHREN ZU DESSEN HERSTELLUNG | [2022/19] | English: | MEMORY DIE WITH DIRECT INTEGRATION TO LOGIC DIE AND METHOD OF MANUFACTURING THE SAME | [2022/19] | French: | PUCE DE MEMOIRE AVEC INTEGRATION DIRECTE A UNE PUCE LOGIQUE ET SON PROCEDE DE FABRICATION | [2022/19] |
Former [2017/16] | VERFAHREN ZUR DIREKTEN INTEGRATION EINES SPEICHERCHIPS ZU EINEM LOGISCHEN CHIP OHNE VERWENDUNG VON SILICIUMDURCHKONTAKTIERUNG (TSV) | ||
Former [2017/16] | METHOD FOR DIRECT INTEGRATION OF MEMORY DIE TO LOGIC DIE WITHOUT USE OF THROUGH SILICON VIAS (TSV) | ||
Former [2017/16] | PROCÉDÉ D'INTÉGRATION DIRECTE DE PUCES DE MÉMOIRE DANS UNE MATRICE LOGIQUE SANS UTILISATION DE TROUS D'INTERCONNEXION TRAVERSANTS EN SILICIUM (TSV) | Entry into regional phase | 04.11.2016 | National basic fee paid | 04.11.2016 | Search fee paid | 04.11.2016 | Designation fee(s) paid | 04.11.2016 | Examination fee paid | Examination procedure | 04.11.2016 | Examination requested [2017/16] | 04.11.2016 | Date on which the examining division has become responsible | 23.08.2018 | Amendment by applicant (claims and/or description) | 07.07.2020 | Despatch of a communication from the examining division (Time limit: M04) | 17.11.2020 | Reply to a communication from the examining division | 05.04.2022 | Cancellation of oral proceeding that was planned for 06.04.2022 | 06.04.2022 | Date of oral proceedings (cancelled) | 02.05.2022 | Communication of intention to grant the patent | 04.08.2022 | Disapproval of the communication of intention to grant the patent by the applicant or resumption of examination proceedings by the EPO | 04.08.2022 | Fee for grant paid | 04.08.2022 | Fee for publishing/printing paid | 05.09.2022 | Communication of intention to grant the patent | 12.01.2023 | Receipt of the translation of the claim(s) | Opposition(s) | 23.11.2023 | No opposition filed within time limit [2024/05] | Fees paid | Renewal fee | 04.11.2016 | Renewal fee patent year 03 | 16.06.2017 | Renewal fee patent year 04 | 12.06.2018 | Renewal fee patent year 05 | 13.06.2019 | Renewal fee patent year 06 | 15.06.2020 | Renewal fee patent year 07 | 14.06.2021 | Renewal fee patent year 08 | 26.05.2022 | Renewal fee patent year 09 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | AT | 22.02.2023 | CZ | 22.02.2023 | DK | 22.02.2023 | EE | 22.02.2023 | ES | 22.02.2023 | FI | 22.02.2023 | HR | 22.02.2023 | IT | 22.02.2023 | LT | 22.02.2023 | LV | 22.02.2023 | MC | 22.02.2023 | PL | 22.02.2023 | RO | 22.02.2023 | RS | 22.02.2023 | SE | 22.02.2023 | SI | 22.02.2023 | SK | 22.02.2023 | SM | 22.02.2023 | NO | 22.05.2023 | GR | 23.05.2023 | IE | 16.06.2023 | LU | 16.06.2023 | IS | 22.06.2023 | PT | 22.06.2023 | BE | 30.06.2023 | CH | 30.06.2023 | [2024/26] |
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IE | 16.06.2023 | ||
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IE | 16.06.2023 | ||
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LU | 16.06.2023 | ||
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LT | 22.02.2023 | Documents cited: | Search | [XI]US2010314711 (FAROOQ MUKTA G [US], et al) [X] 1-3,7-11,15 * paragraph [0012] - paragraph [0036]; figures 1-12 * [I] 4-6,12-14; | [XI]US2013021060 (OR-BACH ZVI [US]) [X] 1,2,4-15 * paragraph [0019] - paragraph [0045] * * paragraph [0198] - paragraph [0231]; figures 8,16,18,19 * * paragraph [0393] - paragraph [0405]; figure 83 * * paragraph [0450] * * paragraph [0530] *[I] 3 | International search | [Y]US2005218521 (LEE SANG-YUN [US]) [Y] 15 * See abstract, paragraph [0052] and figure 2. *; | [XYA]US2009224364 (OH CHOONSIK [KR], et al) [X] 10-11 * See abstract, paragraphs [0041]-[0093], claim 19 and figures 1-12. * [Y] 15 [A] 1-8, 12-14, 16-19; | [A]US2010081232 (FURMAN BRUCE K [US], et al) [A] 1-8, 10-19 * See abstract, paragraphs [0028]-[0033], claim 1 and figure 2. *; | [A]US2013168674 (FRANZON PAUL D [US], et al) [A] 1-8, 10-19 * See abstract, paragraphs [0013]-[0014] and figure 1. *; | [A]US2014117470 (BASKARAN RAJASHREE [US], et al) [A] 1-8, 10-19* See abstract, paragraphs [0019]-[0043] and claim 31. * |