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Extract from the Register of European Patents

EP About this file: EP3182444

EP3182444 - METHOD FOR REDUCING LOSS OF SILICON CAP LAYER OVER SIGE SOURCE/DRAIN IN A CMOS DEVICE [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  27.11.2020
Database last updated on 05.10.2024
FormerExamination is in progress
Status updated on  24.03.2020
FormerRequest for examination was made
Status updated on  22.09.2017
FormerThe application has been published
Status updated on  19.05.2017
Most recent event   Tooltip27.11.2020Application deemed to be withdrawnpublished on 30.12.2020  [2020/53]
Applicant(s)For all designated states
Semiconductor Manufacturing International (Shanghai) Corporation
No. 18, Zhangjiang Road
Pudong New Area
Shanghai 201203 / CN
For all designated states
Semiconductor Manufacturing International (Beijing) Corporation
No. 18, Wenchang Road
Beijing Economic and Technological
Development Area, Daxing Area
Beijing 100176 / CN
[2018/45]
Former [2017/31]For all designated states
Semiconductor Manufacturing International Corporation (Shanghai)
No. 18, Zhangjiang Road
Pudong New Area
Shanghai 201203 / CN
For all designated states
Semiconductor Manufacturing International Corporation (Beijing)
No. 18, Wenchang Road
Beijing Economic and Technological
Development Area, Daxing Area
Beijing 100176 / CN
Former [2017/25]For all designated states
Semiconductor Manufacturing International Corporation (Shanghai)
No. 18, Zhangjiang Road
Pudong New Area
Shanghai 201203 / CN
For all designated states
Semiconductor Manufacturing International Corporation (Beijing)
No. 18, Wenchang Road
Economic and Technological
Development Area, Daxing Area
Beijing 1000176 / CN
Inventor(s)01 / LIU, Jialei
c/o Semiconductor Manufacturing International
Corporation (Shanghai)
Mr. Wentian ZHANG
No. 18, Zhangjiang Road, Pudong New Area
Shanghai, 201203 / CN
 [2017/25]
Representative(s)Klunker IP Patentanwälte PartG mbB
Destouchesstraße 68
80796 München / DE
[2017/25]
Application number, filing date16202837.708.12.2016
[2017/25]
Priority number, dateCN20151093976615.12.2015         Original published format: CN201510939766
[2017/25]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP3182444
Date:21.06.2017
Language:EN
[2017/25]
Search report(s)(Supplementary) European search report - dispatched on:EP18.04.2017
ClassificationIPC:H01L21/8238
[2017/25]
CPC:
H01L21/823814 (EP,US); H01L21/8238 (CN); H01L21/823807 (CN);
H01L21/823864 (EP,US); H01L27/092 (US); H01L29/0847 (US);
H01L29/161 (US); H01L29/165 (US); H01L29/7845 (CN);
H01L29/7848 (US) (-)
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2017/43]
Former [2017/25]AL,  AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MK,  MT,  NL,  NO,  PL,  PT,  RO,  RS,  SE,  SI,  SK,  SM,  TR 
Extension statesBANot yet paid
MENot yet paid
Validation statesMANot yet paid
MDNot yet paid
TitleGerman:VERFAHREN ZUR REDUZIERUNG DES VERLUSTES EINER SILICIUMDECKSCHICHT ÜBER SIGE-SOURCE-/DRAIN BEI EINER CMOS-VORRICHTUNG[2017/25]
English:METHOD FOR REDUCING LOSS OF SILICON CAP LAYER OVER SIGE SOURCE/DRAIN IN A CMOS DEVICE[2017/25]
French:PROCÉDÉ POUR RÉDUIRE LES PERTES DE COUCHE DE PROTECTION EN SILICIUM SUR SOURCE/DRAIN EN SIGE DANS UN DISPOSITIF CMOS[2017/25]
Examination procedure08.12.2016Date on which the examining division has become responsible
15.09.2017Amendment by applicant (claims and/or description)
15.09.2017Examination requested  [2017/43]
27.03.2020Despatch of a communication from the examining division (Time limit: M04)
07.08.2020Application deemed to be withdrawn, date of legal effect  [2020/53]
27.08.2020Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [2020/53]
Fees paidRenewal fee
19.12.2018Renewal fee patent year 03
23.12.2019Renewal fee patent year 04
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Documents cited:Search[Y]US2008124922  (KAWAMURA KAZUO [JP], et al) [Y] 1-15 * paragraph [0070]; figures 8-10 *;
 [Y]US2011070701  (NING XIAN JIE [CN], et al) [Y] 1-15 * paragraphs [0054] - [0069]; figures 4-10 *;
 [A]US2011201166  (CHUNG HOI-SUNG [KR], et al) [A] 1* paragraph [0112]; figures 9-16 *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.