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Extract from the Register of European Patents

EP About this file: EP3633529

EP3633529 - SYSTEMC MODEL GENERATION METHOD AND SYSTEMC MODEL GENERATION PROGRAM [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  30.04.2021
Database last updated on 07.10.2024
FormerRequest for examination was made
Status updated on  06.03.2020
FormerThe international publication has been made
Status updated on  08.12.2018
Most recent event   Tooltip30.04.2021Application deemed to be withdrawnpublished on 02.06.2021  [2021/22]
Applicant(s)For all designated states
Fujitsu Limited
1-1, Kamikodanaka 4-chome
Nakahara-ku
Kawasaki-shi, Kanagawa 211-8588 / JP
[2020/15]
Inventor(s)01 / YAMASHITA, Hiroaki
c/o Fujitsu Kyushu Network Technologies Limited
2-1 momochihama 2-chome
sawara-ku
fukuoka-shi Fukuoka 814-8588 / JP
02 / IMAZATO, Kenichi
c/o Fujitsu Kyushu Network Technologies Limited
2-1 momochihama 2-chome
sawara-ku
fukuoka-shi Fukuoka 814-8588 / JP
03 / TAMIYA, Yutaka
c/o FUJITSU LIMITED
1-1 Kamikodanaka 4-chome
Nakahara-ku
Kawasaki-shi Kanagawa 211-8588 / JP
 [2020/15]
Representative(s)Hoffmann Eitle
Patent- und Rechtsanwälte PartmbB
Arabellastraße 30
81925 München / DE
[2020/15]
Application number, filing date18809491.628.03.2018
[2020/15]
WO2018JP12695
Priority number, dateJP2017010581429.05.2017         Original published format: JP 2017105814
[2020/15]
Filing languageJA
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO2018220974
Date:06.12.2018
Language:JA
[2018/49]
Type: A1 Application with search report 
No.:EP3633529
Date:08.04.2020
Language:EN
[2020/15]
Search report(s)International search report - published on:JP06.12.2018
(Supplementary) European search report - dispatched on:EP06.05.2020
ClassificationIPC:G06F30/323
[2020/23]
CPC:
G06F16/9027 (EP); G06F30/327 (EP,US); G06F16/903 (US);
G06F30/33 (EP,US)
Former IPC [2020/15]G06F17/50
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2020/15]
TitleGerman:SYSTEMMODELLERZEUGUNGSVERFAHREN UND SYSTEMMODELLERZEUGUNGSPROGRAMM[2020/15]
English:SYSTEMC MODEL GENERATION METHOD AND SYSTEMC MODEL GENERATION PROGRAM[2020/15]
French:PROCÉDÉ DE GÉNÉRATION D'UN MODÈLE SYSTEMC ET PROGRAMME DE GÉNÉRATION D'UN MODÈLE SYSTEMC[2020/15]
Entry into regional phase23.10.2019Translation filed 
23.10.2019National basic fee paid 
23.10.2019Search fee paid 
23.10.2019Designation fee(s) paid 
23.10.2019Examination fee paid 
Examination procedure23.10.2019Amendment by applicant (claims and/or description)
23.10.2019Examination requested  [2020/15]
08.12.2020Application deemed to be withdrawn, date of legal effect  [2021/22]
14.01.2021Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [2021/22]
Fees paidRenewal fee
02.01.2020Renewal fee patent year 03
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[XI]  - Gert Jan Schoneveld, "VHDL to SystemC: The Design of a Translator", (20090827), URL: https://repository.tudelft.nl/islandora/object/uuid%3Af2ecf719-d8d4-4197-be07-1822e84f6968, (20200424), XP055689141 [X] 1-5,10,12-15 * abstract * * pages 23-27; figure 3.1. * [I] 6-9,11
 [XI]  - YUN-HUNG LIAW ET AL, "V2X: An Automated Tool for Building SystemC-Based Simulation Environments in Designing Multicore Systems-on-Chips", PARALLEL AND DISTRIBUTED PROCESSING WITH APPLICATIONS (ISPA), 2010 INTERNATIONAL SYMPOSIUM ON, IEEE, PISCATAWAY, NJ, USA, (20100906), ISBN 978-1-4244-8095-1, pages 413 - 418, XP031800413 [X] 1-5,10,12-15 * abstract * * section III. * [I] 6-9,11
 [A]  - BOMBANA M ET AL, "SystemC-VHDL Co-simulation and synthesis in the HW domain", DESIGN, AUTOMATION, AND TEST IN EUROPE CONFERENCE AND EXHIBITION. PROCEEDINGS, IEEE COMPUTER SOCIETY, US, (20030303), ISSN 1530-1591, ISBN 978-0-7695-2288-3, pages 101 - 105, XP010674170 [A] 1-15 * abstract * * section 2.;; figure 1 *
 [A]  - Chris Fletcher, "Verilog: always @ Blocks", (20090827), URL: https://inst.eecs.berkeley.edu/~eecs151/fa19/files/verilog/always_at_blocks.pdf, (20200424), XP055689277 [A] 1-15 * the whole document *
International search[A]JP2007087215  (HITACHI LTD) [A] 1-16 * , paragraphs [0014]-[0027], [0065] & US 2007/0067751 A1, paragraphs [0119]-[0132], [0189]-[0209] *;
 [A]JP2008077330  (FUJITSU LTD) [A] 1-16 * , paragraphs [0005]-[0040] & US 2008/0071514 A1, paragraphs [0008]-[0056] *;
 [A]  - TATSUOKA, MASATO et al., "Function Code Extraction from RTL Property for Reuse", IEICE technical report, (20140224), vol. 113, no. 454, ISSN 0913-5685, pages 171 - 176, XP055640838 [A] 1-16
by applicantJP2013020329
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.