EP3671826 - IMPROVED METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT COMPRISING AN NMOS TRANSISTOR AND A PMOS TRANSISTOR [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 05.04.2024 Database last updated on 16.07.2024 | |
Former | The patent has been granted Status updated on 28.04.2023 | ||
Former | Grant of patent is intended Status updated on 13.12.2022 | ||
Former | Request for examination was made Status updated on 22.05.2020 | Most recent event Tooltip | 24.05.2024 | Lapse of the patent in a contracting state New state(s): IT | published on 26.06.2024 [2024/26] | Applicant(s) | For all designated states COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES 25, Rue Leblanc Bâtiment "Le Ponant D" 75015 Paris / FR | [2020/26] | Inventor(s) | 01 /
POSSEME, Nicolas c/o CEA Grenoble 17 rue des Martyrs 38054 Grenoble Cedex 09 / FR | 02 /
GABEN, Loïc c/o CEA Grenoble 17 rue des Martyrs 38054 Grenoble Cedex 09 / FR | 03 /
LE ROYER, Cyrille c/o CEA Grenoble 17 rue des Martyrs 38054 Grenoble Cedex 09 / FR | 04 /
NEMOUCHI, Fabrice c/o CEA Grenoble 17 rue des Martyrs 38054 Grenoble Cedex 09 / FR | 05 /
REBOH, Shay c/o CEA Grenoble 17 rue des Martyrs 38054 Grenoble Cedex 09 / FR | [2020/26] | Representative(s) | Guérin, Jean-Philippe Innovation Competence Group 310 avenue Berthelot 69372 Lyon Cedex 08 / FR | [2020/26] | Application number, filing date | 19215347.6 | 11.12.2019 | [2020/26] | Priority number, date | FR20180073216 | 18.12.2018 Original published format: FR 1873216 | [2020/26] | Filing language | FR | Procedural language | FR | Publication | Type: | A1 Application with search report | No.: | EP3671826 | Date: | 24.06.2020 | Language: | FR | [2020/26] | Type: | B1 Patent specification | No.: | EP3671826 | Date: | 31.05.2023 | Language: | FR | [2023/22] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 23.04.2020 | Classification | IPC: | H01L21/84, H01L27/12, H01L21/8238 | [2020/26] | CPC: |
H01L21/84 (EP,US);
H01L21/02381 (US);
H01L21/02488 (US);
H01L21/02532 (US);
H01L21/02694 (US);
H01L21/823807 (EP,US);
H01L27/1203 (EP)
(-)
| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2020/26] | Title | German: | VERBESSERTES HERSTELLUNGSVERFAHREN EINES INTEGRIERTEN SCHALTKREISES, DER EINEN NMOS- UND EINEN PMOS-TRANSISTOR UMFASST | [2020/26] | English: | IMPROVED METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT COMPRISING AN NMOS TRANSISTOR AND A PMOS TRANSISTOR | [2020/26] | French: | PROCÉDÉ AMÉLIORÉ DE FABRICATION D'UN CIRCUIT INTÉGRÉ COMPORTANT UN TRANSISTOR NMOS ET UN TRANSISTOR PMOS | [2020/26] | Examination procedure | 11.12.2019 | Examination requested [2020/26] | 30.10.2020 | Amendment by applicant (claims and/or description) | 14.12.2022 | Communication of intention to grant the patent | 17.04.2023 | Fee for grant paid | 17.04.2023 | Fee for publishing/printing paid | 17.04.2023 | Receipt of the translation of the claim(s) | Divisional application(s) | EP23175870.7 / EP4235765 | Opposition(s) | 01.03.2024 | No opposition filed within time limit [2024/19] | Fees paid | Renewal fee | 30.11.2021 | Renewal fee patent year 03 | 21.12.2022 | Renewal fee patent year 04 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | AT | 31.05.2023 | CZ | 31.05.2023 | DK | 31.05.2023 | EE | 31.05.2023 | ES | 31.05.2023 | FI | 31.05.2023 | HR | 31.05.2023 | IT | 31.05.2023 | LT | 31.05.2023 | LV | 31.05.2023 | NL | 31.05.2023 | PL | 31.05.2023 | RO | 31.05.2023 | RS | 31.05.2023 | SE | 31.05.2023 | SI | 31.05.2023 | SK | 31.05.2023 | SM | 31.05.2023 | NO | 31.08.2023 | GR | 01.09.2023 | IS | 30.09.2023 | PT | 02.10.2023 | [2024/26] |
Former [2024/25] | AT | 31.05.2023 | |
CZ | 31.05.2023 | ||
DK | 31.05.2023 | ||
EE | 31.05.2023 | ||
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FI | 31.05.2023 | ||
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SM | 31.05.2023 | ||
NO | 31.08.2023 | ||
GR | 01.09.2023 | ||
IS | 30.09.2023 | ||
PT | 02.10.2023 | ||
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SK | 31.05.2023 | ||
SM | 31.05.2023 | ||
NO | 31.08.2023 | ||
GR | 01.09.2023 | ||
IS | 30.09.2023 | ||
PT | 02.10.2023 | ||
Former [2024/08] | AT | 31.05.2023 | |
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SM | 31.05.2023 | ||
NO | 31.08.2023 | ||
GR | 01.09.2023 | ||
IS | 30.09.2023 | ||
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NO | 31.08.2023 | ||
GR | 01.09.2023 | ||
IS | 30.09.2023 | ||
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NO | 31.08.2023 | ||
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SE | 31.05.2023 | ||
NO | 31.08.2023 | ||
GR | 01.09.2023 | ||
IS | 30.09.2023 | ||
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NO | 31.08.2023 | ||
Former [2023/46] | ES | 31.05.2023 | Documents cited: | Search | [A]EP1968103 (COMMISSARIAT ENERGIE ATOMIQUE [FR]) [A] 1-13 * abstract * * paragraphs [0018] , [0019] , [0024] , [0027] , [0028] *; | [IA]US2012068267 (BEDELL STEPHEN W [US], et al) [I] 1-8,11-13 * abstract * * paragraphs [0015] - [0027] * [A] 9,10; | [A]EP2782118 (ST MICROELECTRONICS CROLLES 2 [FR], et al) [A] 1-13* abstract *; | [A]US2015099335 (LIU QING [US], et al) [A] 1-13 * abstract * * paragraphs [0020] - [0026] *; | [A]US2017309483 (REBOH SHAY [FR], et al) [A] 1-13 * abstract * * paragraphs [0056] , [0068] - [0069] - [0076] , [0079] , [0092] - [0111] * |