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Extract from the Register of European Patents

EP About this file: EP3671826

EP3671826 - IMPROVED METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT COMPRISING AN NMOS TRANSISTOR AND A PMOS TRANSISTOR [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  05.04.2024
Database last updated on 16.07.2024
FormerThe patent has been granted
Status updated on  28.04.2023
FormerGrant of patent is intended
Status updated on  13.12.2022
FormerRequest for examination was made
Status updated on  22.05.2020
Most recent event   Tooltip24.05.2024Lapse of the patent in a contracting state
New state(s): IT
published on 26.06.2024  [2024/26]
Applicant(s)For all designated states
COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
25, Rue Leblanc
Bâtiment "Le Ponant D"
75015 Paris / FR
[2020/26]
Inventor(s)01 / POSSEME, Nicolas
c/o CEA Grenoble
17 rue des Martyrs
38054 Grenoble Cedex 09 / FR
02 / GABEN, Loïc
c/o CEA Grenoble
17 rue des Martyrs
38054 Grenoble Cedex 09 / FR
03 / LE ROYER, Cyrille
c/o CEA Grenoble
17 rue des Martyrs
38054 Grenoble Cedex 09 / FR
04 / NEMOUCHI, Fabrice
c/o CEA Grenoble
17 rue des Martyrs
38054 Grenoble Cedex 09 / FR
05 / REBOH, Shay
c/o CEA Grenoble
17 rue des Martyrs
38054 Grenoble Cedex 09 / FR
 [2020/26]
Representative(s)Guérin, Jean-Philippe
Innovation Competence Group
310 avenue Berthelot
69372 Lyon Cedex 08 / FR
[2020/26]
Application number, filing date19215347.611.12.2019
[2020/26]
Priority number, dateFR2018007321618.12.2018         Original published format: FR 1873216
[2020/26]
Filing languageFR
Procedural languageFR
PublicationType: A1 Application with search report 
No.:EP3671826
Date:24.06.2020
Language:FR
[2020/26]
Type: B1 Patent specification 
No.:EP3671826
Date:31.05.2023
Language:FR
[2023/22]
Search report(s)(Supplementary) European search report - dispatched on:EP23.04.2020
ClassificationIPC:H01L21/84, H01L27/12, H01L21/8238
[2020/26]
CPC:
H01L21/84 (EP,US); H01L21/02381 (US); H01L21/02488 (US);
H01L21/02532 (US); H01L21/02694 (US); H01L21/823807 (EP,US);
H01L27/1203 (EP) (-)
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2020/26]
TitleGerman:VERBESSERTES HERSTELLUNGSVERFAHREN EINES INTEGRIERTEN SCHALTKREISES, DER EINEN NMOS- UND EINEN PMOS-TRANSISTOR UMFASST[2020/26]
English:IMPROVED METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT COMPRISING AN NMOS TRANSISTOR AND A PMOS TRANSISTOR[2020/26]
French:PROCÉDÉ AMÉLIORÉ DE FABRICATION D'UN CIRCUIT INTÉGRÉ COMPORTANT UN TRANSISTOR NMOS ET UN TRANSISTOR PMOS[2020/26]
Examination procedure11.12.2019Examination requested  [2020/26]
30.10.2020Amendment by applicant (claims and/or description)
14.12.2022Communication of intention to grant the patent
17.04.2023Fee for grant paid
17.04.2023Fee for publishing/printing paid
17.04.2023Receipt of the translation of the claim(s)
Divisional application(s)EP23175870.7  / EP4235765
Opposition(s)01.03.2024No opposition filed within time limit [2024/19]
Fees paidRenewal fee
30.11.2021Renewal fee patent year 03
21.12.2022Renewal fee patent year 04
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Patent Court
See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT31.05.2023
CZ31.05.2023
DK31.05.2023
EE31.05.2023
ES31.05.2023
FI31.05.2023
HR31.05.2023
IT31.05.2023
LT31.05.2023
LV31.05.2023
NL31.05.2023
PL31.05.2023
RO31.05.2023
RS31.05.2023
SE31.05.2023
SI31.05.2023
SK31.05.2023
SM31.05.2023
NO31.08.2023
GR01.09.2023
IS30.09.2023
PT02.10.2023
[2024/26]
Former [2024/25]AT31.05.2023
CZ31.05.2023
DK31.05.2023
EE31.05.2023
ES31.05.2023
FI31.05.2023
HR31.05.2023
LT31.05.2023
LV31.05.2023
NL31.05.2023
PL31.05.2023
RO31.05.2023
RS31.05.2023
SE31.05.2023
SI31.05.2023
SK31.05.2023
SM31.05.2023
NO31.08.2023
GR01.09.2023
IS30.09.2023
PT02.10.2023
Former [2024/10]AT31.05.2023
CZ31.05.2023
DK31.05.2023
EE31.05.2023
ES31.05.2023
FI31.05.2023
HR31.05.2023
LT31.05.2023
LV31.05.2023
NL31.05.2023
PL31.05.2023
RO31.05.2023
RS31.05.2023
SE31.05.2023
SK31.05.2023
SM31.05.2023
NO31.08.2023
GR01.09.2023
IS30.09.2023
PT02.10.2023
Former [2024/08]AT31.05.2023
ES31.05.2023
FI31.05.2023
HR31.05.2023
LT31.05.2023
LV31.05.2023
NL31.05.2023
PL31.05.2023
RS31.05.2023
SE31.05.2023
SK31.05.2023
SM31.05.2023
NO31.08.2023
GR01.09.2023
IS30.09.2023
Former [2024/03]AT31.05.2023
ES31.05.2023
FI31.05.2023
HR31.05.2023
LT31.05.2023
LV31.05.2023
NL31.05.2023
PL31.05.2023
RS31.05.2023
SE31.05.2023
NO31.08.2023
GR01.09.2023
IS30.09.2023
Former [2024/01]AT31.05.2023
ES31.05.2023
HR31.05.2023
LT31.05.2023
LV31.05.2023
NL31.05.2023
PL31.05.2023
RS31.05.2023
SE31.05.2023
NO31.08.2023
GR01.09.2023
IS30.09.2023
Former [2023/52]AT31.05.2023
ES31.05.2023
HR31.05.2023
NL31.05.2023
PL31.05.2023
RS31.05.2023
SE31.05.2023
NO31.08.2023
GR01.09.2023
IS30.09.2023
Former [2023/51]AT31.05.2023
ES31.05.2023
HR31.05.2023
PL31.05.2023
RS31.05.2023
SE31.05.2023
NO31.08.2023
GR01.09.2023
IS30.09.2023
Former [2023/50]AT31.05.2023
ES31.05.2023
PL31.05.2023
SE31.05.2023
NO31.08.2023
GR01.09.2023
IS30.09.2023
Former [2023/48]AT31.05.2023
ES31.05.2023
SE31.05.2023
NO31.08.2023
Former [2023/46]ES31.05.2023
Documents cited:Search[A]EP1968103  (COMMISSARIAT ENERGIE ATOMIQUE [FR]) [A] 1-13 * abstract * * paragraphs [0018] , [0019] , [0024] , [0027] , [0028] *;
 [IA]US2012068267  (BEDELL STEPHEN W [US], et al) [I] 1-8,11-13 * abstract * * paragraphs [0015] - [0027] * [A] 9,10;
 [A]EP2782118  (ST MICROELECTRONICS CROLLES 2 [FR], et al) [A] 1-13* abstract *;
 [A]US2015099335  (LIU QING [US], et al) [A] 1-13 * abstract * * paragraphs [0020] - [0026] *;
 [A]US2017309483  (REBOH SHAY [FR], et al) [A] 1-13 * abstract * * paragraphs [0056] , [0068] - [0069] - [0076] , [0079] , [0092] - [0111] *
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