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Extract from the Register of European Patents

EP About this file: EP3846222

EP3846222 - JUNCTION FIELD-EFFECT TRANSISTOR, METHOD FOR OBTAINING SAME AND USE THEREOF [Right-click to bookmark this link]
StatusRequest for examination was made
Status updated on  04.06.2021
Database last updated on 07.10.2024
FormerThe international publication has been made
Status updated on  07.03.2020
Most recent event   Tooltip02.08.2023New entry: Renewal fee paid 
Applicant(s)For all designated states
Consejo Superior De Investigaciones Científicas
C/ Serrano 117
28006 Madrid / ES
[2021/27]
Inventor(s)01 / ULLÁN COMES, Miguel
Instituto de Microelectrónica
de Barcelona
Campus UAB
Carrer dels Til·lers
08193 Cerdanyola del Vallès (Barcelona) / ES
02 / COUSO FONTANILLO, Carlos
Instituto de Microelectrónica
de Barcelona
Campus UAB
Carrer dels Til·lers
08193 Cerdanyola del Vallès (Barcelona) / ES
03 / HIDALGO VILLENA, Salvador
Instituto de Microelectrónica
de Barcelona
Campus UAB
Carrer dels Til·lers
08193 Cerdanyola del Vallès (Barcelona) / ES
04 / FLORES GUAL, David
Instituto de Microelectrónica
de Barcelona
Campus UAB
Carrer dels Til·lers
08193 Cerdanyola del Vallès (Barcelona) / ES
05 / QUIRION, David
Instituto de Microelectrónica
de Barcelona
Campus UAB
Carrer dels Til·lers
08193 Cerdanyola del Vallès (Barcelona) / ES
 [2021/27]
Representative(s)Pons
Glorieta Rubén Darío 4
28010 Madrid / ES
[N/P]
Former [2021/27]Pons
Glorieta Ruben Dario 4
28010 Madrid / ES
Application number, filing date19854146.829.08.2019
[2021/27]
WO2019ES70578
Priority number, dateES2018003086031.08.2018         Original published format: ES 201830860
[2021/27]
Filing languageES
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO2020043927
Date:05.03.2020
Language:ES
[2020/10]
Type: A1 Application with search report 
No.:EP3846222
Date:07.07.2021
Language:EN
[2021/27]
Search report(s)International search report - published on:ES05.03.2020
(Supplementary) European search report - dispatched on:EP20.04.2022
ClassificationIPC:H01L29/808, H01L21/337, H01L29/06, H01L29/10, H01L21/02, H01L21/70, H01L23/552, H01L29/772
[2022/19]
CPC:
H01L29/8083 (EP); H01L29/772 (ES); H01L21/02 (ES);
H01L21/70 (ES); H01L23/552 (ES); H01L23/585 (EP);
H01L23/62 (EP); H01L29/0619 (EP); H01L29/0696 (EP);
H01L29/1066 (EP); H01L29/66909 (EP) (-)
Former IPC [2021/27]H01L29/772, H01L21/02, H01L21/70, H01L23/552
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2021/27]
TitleGerman:SPERRSCHICHT-FELDEFFEKTTRANSISTOR, VERFAHREN ZU SEINER HERSTELLUNG UND SEINE VERWENDUNG[2021/27]
English:JUNCTION FIELD-EFFECT TRANSISTOR, METHOD FOR OBTAINING SAME AND USE THEREOF[2021/27]
French:TRANSISTOR À EFFET DE CHAMP À JONCTION, SON PROCÉDÉ D'OBTENTION ET SON UTILISATION[2021/27]
Entry into regional phase02.03.2021Translation filed 
02.03.2021National basic fee paid 
02.03.2021Search fee paid 
02.03.2021Designation fee(s) paid 
02.03.2021Examination fee paid 
Examination procedure02.03.2021Examination requested  [2021/27]
04.11.2022Amendment by applicant (claims and/or description)
Fees paidRenewal fee
13.08.2021Renewal fee patent year 03
27.02.2023Renewal fee patent year 04
02.08.2023Renewal fee patent year 05
Penalty fee
Additional fee for renewal fee
31.08.202204   M06   Fee paid on   27.02.2023
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Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[A]JP2001332727  (FUJI ELECTRIC CO LTD) [A] 1-11 * figure 2 *;
 [A]US2003047776  (HUETING RAYMOND J E [NL], et al) [A] 1-11* figure 11 *;
 [A]JP2005286042  (TOYOTA MOTOR CORP, et al) [A] 1-11 * figure 1 *;
 [A]US2013313568  (HAYASHI HIDEKI [JP], et al) [A] 1-11 * figure 3 *;
 [A]WO2017051051  (CONSEJO SUPERIOR DE INVESTIG CIENTÍFICAS (CSIC) [ES]) [A] 1-11 * figures 1-7 *;
 [A]US2017133518  (LI ZHONGDA [US], et al) [A] 1-11 * figure 3 *;
 [A]  - FERNANDEZ-MARTINEZ PABLO ET AL, "A new vertical JFET technology for the powering scheme of the ATLAS upgrade inner tracker", 2016 IEEE NUCLEAR SCIENCE SYMPOSIUM, MEDICAL IMAGING CONFERENCE AND ROOM-TEMPERATURE SEMICONDUCTOR DETECTOR WORKSHOP (NSS/MIC/RTSD), IEEE, (20161029), doi:10.1109/NSSMIC.2016.8069654, pages 1 - 4, XP033228107 [A] 1-11 * figures 1,3,4 *

DOI:   http://dx.doi.org/10.1109/NSSMIC.2016.8069654
 [A]  - Victor Veliadis ET AL, "Fabrication of a robust high-performance floating guard ring edge termination for power Silicon Carbide Vertical Junction Field Effect Transistors", 22nd International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2007, (20070101), pages 217 - 220, URL: https://pdfs.semanticscholar.org/952f/1210dd385920edcff9353d15b196403a49ef.pdf?_ga=2.252406089.1529710891.1589458046-952773486.1586340753, (20200514), XP055695510 [A] 1-11 * figures 2-4 *
International search[A]US5963807  (UENO KATSUNORI [JP]) [A] 1-11* , column 1, lines 9-15; column 7, line 6-column 10, line 29. *;
 [A]WO2017051051  (CONSEJO SUPERIOR DE INVESTIG CIENTÍFICAS (CSIC) [ES]) [A] 1-11 * , page 3, line 33-page 5, line 17; page 6, line 3-page 8, line 34; figures. *;
 [A]  - FERNANDEZ-MARTINEZ, P. et al., "A new vertical JFET technology for the powering scheme of the ATLAS upgrade inner tracker", 2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop, NSS/MIC/RTSD 2016, (20160000), XP033228107 [A] 1-11

DOI:   http://dx.doi.org/10.1109/NSSMIC.2016.8069654
 [A]  - VELLVEHI, M. et al., "Failure Analysis in Power Devices using Lock-in Infrared Thermography. 2018. 19th International Conference on Thermal", 2018 19th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), (20180400), pages 1 - 7, XP033351905 [A] 1-11

DOI:   http://dx.doi.org/10.1109/EuroSimE.2018.8369896
 [A]  - VELIADIS, V. et al., "Fabrication of a robust high-performance floating guard ring edge termination for power Silicon Carbide Vertical Junction Field Effect Transistors", 22nd International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2007, vol. 2007, pages 217 - 220, URL: https://pdfs.semanticscholar.org/952f/1210dd385920edcff9353d15b196403a49ef.pdf?_ga=2.252406089.1529710891.1589458046-952773486.1586340753, (20190531), XP055695510 [A] 1-11
by applicantUS6251716
 US6380569
 US2009075435
 US8068321
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.