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Extract from the Register of European Patents

EP About this file: EP3886104

EP3886104 - RESISTIVE RANDOM MEMORY ARCHITECTURE WITH HIGH INTEGRATION DENSITY AND CONTROL METHOD THEREOF [Right-click to bookmark this link]
StatusThe patent has been granted
Status updated on  22.12.2023
Database last updated on 30.10.2024
FormerGrant of patent is intended
Status updated on  05.09.2023
FormerRequest for examination was made
Status updated on  18.03.2022
FormerThe application has been published
Status updated on  27.08.2021
Most recent event   Tooltip25.10.2024Lapse of the patent in a contracting state
New state(s): CZ, EE		published on 27.11.2024 [2024/48]
Applicant(s)For all designated states
Centre National de la Recherche Scientifique
3, rue Michel-Ange
75016 Paris / FR
For all designated states
Université d'Aix-Marseille
58 Boulevard Charles Livon
13007 Marseille / FR
For all designated states
American University Of Beirut
P.O. Box 11-0236 Riad El Solh
Beirut 1107-2020 / LB
[2024/04]
Former [2021/39]For all designated states
Centre National de la Recherche Scientifique
3 rue Michel-Ange
75016 Paris / FR
For all designated states
Université d'Aix-Marseille
58 Boulevard Charles Livon
13007 Marseille / FR
For all designated states
American University Of Beirut
P.O. Box 11-0236 Riad El Solh
Beirut 1107-2020 / LB
Inventor(s)01 / HAJRI, Basma
American University of Beirut
P.O. Box 11-0236 /FEA/ECE
IOEC Building 5th floor, room 509D
Riad El-Solh
Beirut 1107 2020 / LB
02 / AZIZA, Hassan
5 rue du Taoume A226
13013 MARSEILLE / FR
03 / MANSOUR, Mohammad
Sioufi Towers
3rd Floor, Shiekh Gaby Street
ACHRAFIEH
BEIRUT / LB
04 / CHEHAB, Ali
Bliss Street
ECE Department, AUB
Beirut 1107 2020 / LB
 [2021/39]
Representative(s)Marchand, André, et al
Omnipat
610, chemin de Fabrègues
13510 Éguilles / FR
[2024/04]
Former [2021/39]de Roquemaurel, Bruno, et al
Omnipat
24 place des Martyrs de la Résistance
13100 Aix en Provence / FR
Application number, filing date20166074.326.03.2020
[2021/39]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP3886104
Date:29.09.2021
Language:EN
[2021/39]
Type: B1 Patent specification 
No.:EP3886104
Date:24.01.2024
Language:EN
[2024/04]
Search report(s)(Supplementary) European search report - dispatched on:EP26.08.2020
ClassificationIPC:G11C13/00
[2021/39]
CPC:
G11C13/003 (EP); G11C13/004 (EP); G11C13/0069 (EP)
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2022/16]
Former [2021/39]AL,  AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MK,  MT,  NL,  NO,  PL,  PT,  RO,  RS,  SE,  SI,  SK,  SM,  TR 
TitleGerman:RESISTIVE DIREKTSPEICHERARCHITEKTUR MIT HOHER INTEGRATIONSDICHTE UND STEUERUNGSVERFAHREN DAFÜR[2021/39]
English:RESISTIVE RANDOM MEMORY ARCHITECTURE WITH HIGH INTEGRATION DENSITY AND CONTROL METHOD THEREOF[2021/39]
French:ARCHITECTURE DE MÉMOIRE RÉSISTIVE ALÉATOIRE À HAUTE DENSITÉ D'INTÉGRATION ET SON PROCÉDÉ DE COMMANDE[2021/39]
Examination procedure11.03.2022Amendment by applicant (claims and/or description)
11.03.2022Examination requested  [2022/16]
11.03.2022Date on which the examining division has become responsible
06.09.2023Communication of intention to grant the patent
18.12.2023Fee for grant paid
18.12.2023Fee for publishing/printing paid
18.12.2023Receipt of the translation of the claim(s)
Fees paidRenewal fee
17.03.2022Renewal fee patent year 03
20.03.2023Renewal fee patent year 04
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Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT24.01.2024
BG24.01.2024
CZ24.01.2024
DK24.01.2024
EE24.01.2024
ES24.01.2024
FI24.01.2024
HR24.01.2024
LT24.01.2024
LV24.01.2024
NL24.01.2024
PL24.01.2024
SE24.01.2024
SM24.01.2024
NO24.04.2024
RS24.04.2024
GR25.04.2024
IS24.05.2024
PT24.05.2024
[2024/48]
Former [2024/47]AT24.01.2024
BG24.01.2024
DK24.01.2024
ES24.01.2024
FI24.01.2024
HR24.01.2024
LT24.01.2024
LV24.01.2024
NL24.01.2024
PL24.01.2024
SE24.01.2024
SM24.01.2024
NO24.04.2024
RS24.04.2024
GR25.04.2024
IS24.05.2024
PT24.05.2024
Former [2024/37]AT24.01.2024
BG24.01.2024
ES24.01.2024
FI24.01.2024
HR24.01.2024
LT24.01.2024
LV24.01.2024
NL24.01.2024
PL24.01.2024
SE24.01.2024
NO24.04.2024
RS24.04.2024
GR25.04.2024
IS24.05.2024
PT24.05.2024
Former [2024/36]AT24.01.2024
BG24.01.2024
ES24.01.2024
FI24.01.2024
HR24.01.2024
LT24.01.2024
LV24.01.2024
NL24.01.2024
PL24.01.2024
NO24.04.2024
RS24.04.2024
GR25.04.2024
IS24.05.2024
PT24.05.2024
Former [2024/35]AT24.01.2024
BG24.01.2024
ES24.01.2024
FI24.01.2024
HR24.01.2024
LT24.01.2024
NL24.01.2024
NO24.04.2024
RS24.04.2024
GR25.04.2024
IS24.05.2024
Former [2024/34]BG24.01.2024
FI24.01.2024
HR24.01.2024
LT24.01.2024
NL24.01.2024
NO24.04.2024
RS24.04.2024
GR25.04.2024
IS24.05.2024
Former [2024/33]LT24.01.2024
NL24.01.2024
NO24.04.2024
IS24.05.2024
Former [2024/32]NL24.01.2024
IS24.05.2024
Former [2024/31]NL24.01.2024
Documents cited:Search[XAYI]US2013033923  (KUO HARRY [US], et al) [X] 1,2,5,8,9,11 * paragraph [0034]; figure 2A * * paragraph [0036] - paragraph [0039]; figures 3A, 3B * * paragraph [0048] - paragraph [0055]; figure 6 * [A] 4 [Y] 6,10,12 [I] 3,7,13;
 [IY]US2019080753  (TRAN HIEU VAN [US], et al) [I] 1-13 * paragraph [0004] - paragraph [0006]; figures 2A-2D * * paragraph [0008] - paragraph [0014]; figures 4, 5 * * paragraph [0077]; figure 17 * * paragraph [0117] - paragraph [0118]; figures 31, 32 * [Y] 10,12;
 [IAY]  - CHEN FREDERICK T ET AL, "Write Scheme Allowing Reduced LRS Nonlinearity Requirement in a 3D-RRAM Array With Selector-Less 1TNR Architecture", IEEE ELECTRON DEVICE LETTERS, IEEE, vol. 35, no. 2, doi:10.1109/LED.2013.2294809, ISSN 0741-3106, (20140201), pages 223 - 225, (20140123), XP011538108 [I] 1-3,5,7-9,13 * I. Introduction; page 223; figure 1 * * II Architecture; page 223 - page 224; figure 2 * * III. Write Scheme; page 224 - page 225; figure 3 * [A] 4,10,12 [Y] 6

DOI:   http://dx.doi.org/10.1109/LED.2013.2294809
by applicantUS2016064453
 US2016351623
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.