blank Quick help
blank Maintenance news

Scheduled maintenance

Regular maintenance outages:
between 05.00 and 05.15 hrs CET (Monday to Sunday).

Other outages
Availability
Register Forum

2022.02.11

More...
blank News flashes

News Flashes

New version of the European Patent Register – SPC proceedings information in the Unitary Patent Register.

2024-07-24

More...
blank Related links

Extract from the Register of European Patents

EP About this file: EP4050493

EP4050493 - CIRCUIT AND ELECTRONIC DEVICE [Right-click to bookmark this link]
StatusRequest for examination was made
Status updated on  29.07.2022
Database last updated on 29.07.2024
FormerThe international publication has been made
Status updated on  21.05.2021
Most recent event   Tooltip27.11.2023New entry: Renewal fee paid 
Applicant(s)For all designated states
Huawei Technologies Co., Ltd.
Huawei Administration Building
Bantian, Longgang District
Shenzhen, Guangdong 518129 / CN
[2022/35]
Inventor(s)01 / JIN, Zhigang
Huawei Administration Building Bantian,
Longgang District
Shenzhen, Guangdong 518129 / CN
 [2022/35]
Representative(s)Thun, Clemens
Mitscherlich PartmbB
Patent- und Rechtsanwälte
Karlstraße 7
80333 München / DE
[N/P]
Former [2022/35]Thun, Clemens
Mitscherlich PartmbB
Patent- und Rechtsanwälte
Sonnenstraße 33
80331 München / DE
Application number, filing date20887090.709.11.2020
[2022/35]
WO2020CN127445
Priority number, dateCN20191111443914.11.2019         Original published format: CN201911114439
[2022/35]
Filing languageZH
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO2021093700
Date:20.05.2021
Language:ZH
[2021/20]
Type: A1 Application with search report 
No.:EP4050493
Date:31.08.2022
Language:EN
[2022/35]
Search report(s)International search report - published on:CN20.05.2021
(Supplementary) European search report - dispatched on:EP01.12.2022
ClassificationIPC:G06F15/78, H03K3/037, G11C7/10, G06F1/26, G11C5/14
[2023/01]
CPC:
H03K3/0375 (EP,US); G06F15/7825 (CN); H03K3/037 (US);
G06F1/26 (CN); G11C5/14 (CN); G11C7/1084 (EP,US);
G11C7/1087 (EP,US); H03K3/012 (US); G11C5/147 (EP);
Y02D10/00 (EP) (-)
Former IPC [2022/35]G06F15/78
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2022/35]
TitleGerman:SCHALTUNG UND ELEKTRONISCHES GERÄT[2022/35]
English:CIRCUIT AND ELECTRONIC DEVICE[2022/35]
French:CIRCUIT ET DISPOSITIF ÉLECTRONIQUE[2022/35]
Entry into regional phase23.05.2022Translation filed 
23.05.2022National basic fee paid 
23.05.2022Search fee paid 
23.05.2022Designation fee(s) paid 
23.05.2022Examination fee paid 
Examination procedure23.05.2022Examination requested  [2022/35]
23.06.2023Amendment by applicant (claims and/or description)
23.06.2023Date on which the examining division has become responsible
Fees paidRenewal fee
22.11.2022Renewal fee patent year 03
27.11.2023Renewal fee patent year 04
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court
See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[Y]US2009003500  (LEE KANG YOUL [KR]) [Y] 10 * figures 3,4,5 *;
 [A]US7977975  (LEWIS DAVID [CA], et al) [A] 1,5* figures 6,7 *;
 [XY]KR20110081778  (FUJITSU LTD [JP]) [X] 1,2,5,6,9 * paragraph [0011] - paragraph [0013]; figure 5 * [Y] 3,4,7,8,10;
 [XY]  - STAS FRANCOIS ET AL, "Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits", 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE, (20170528), doi:10.1109/ISCAS.2017.8050571, pages 1 - 4, XP033156175 [X] 1,5 * figures 3(b), 6 * [Y] 3,4,7,8,10

DOI:   http://dx.doi.org/10.1109/ISCAS.2017.8050571
 [Y]  - BEER SALOMON ET AL, "Eleven Ways to Boost Your Synchronizer", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 23, no. 6, doi:10.1109/TVLSI.2014.2331331, ISSN 1063-8210, (20150601), pages 1040 - 1049, (20150520), XP011582162 [Y] 3,7,8 * figure 1 *

DOI:   http://dx.doi.org/10.1109/TVLSI.2014.2331331
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.