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Extract from the Register of European Patents

EP About this file: EP4016598

EP4016598 - GUIDED VIAS IN MICROELECTRONIC STRUCTURES [Right-click to bookmark this link]
StatusRequest for examination was made
Status updated on  16.12.2022
Database last updated on 07.10.2024
FormerThe application has been published
Status updated on  20.05.2022
Most recent event   Tooltip30.08.2024New entry: Renewal fee paid 
Applicant(s)For all designated states
INTEL Corporation
2200 Mission College Blvd.
Santa Clara, CA 95054 / US
[2022/25]
Inventor(s)01 / Singh, Gurpreet
Portland, 97229 / US
02 / Han, Eungnak
Portland, 97229 / US
03 / Chen, Xuanxuan
Hillsboro, 97124 / US
04 / Mahdi, Tayseer
Beaverton, 97006 / US
05 / Krysak, Marie
Portland, 97225 / US
06 / Holybee, Brandon Jay
Portland, 97203 / US
07 / Gstrein, Florian
Portland, 97212 / US
 [2022/25]
Representative(s)Goddar, Heinz J.
Boehmert & Boehmert
Anwaltspartnerschaft mbB
Pettenkoferstrasse 22
80336 München / DE
[2022/25]
Application number, filing date21195439.108.09.2021
[2022/25]
Priority number, dateUS20201712523217.12.2020         Original published format: US202017125232
[2022/25]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP4016598
Date:22.06.2022
Language:EN
[2022/25]
Search report(s)(Supplementary) European search report - dispatched on:EP23.02.2022
ClassificationIPC:H01L21/768, H01L23/522
[2022/25]
CPC:
H01L21/76885 (EP); H01L23/5384 (US); H01L21/76897 (EP);
H01L23/5226 (EP); H01L23/5386 (US); H01L21/76816 (EP);
H01L21/76883 (EP) (-)
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2023/03]
Former [2022/25]AL,  AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MK,  MT,  NL,  NO,  PL,  PT,  RO,  RS,  SE,  SI,  SK,  SM,  TR 
Extension statesBANot yet paid
MENot yet paid
Validation statesKHNot yet paid
MANot yet paid
MDNot yet paid
TNNot yet paid
TitleGerman:GEFÜHRTE DURCHGANGSLÖCHER IN MIKROELEKTRONISCHEN STRUKTUREN[2022/25]
English:GUIDED VIAS IN MICROELECTRONIC STRUCTURES[2022/25]
French:TROUS D'INTERCONNEXION GUIDÉS DANS DES STRUCTURES MICROÉLECTRONIQUES[2022/25]
Examination procedure13.12.2022Amendment by applicant (claims and/or description)
13.12.2022Examination requested  [2023/03]
13.12.2022Date on which the examining division has become responsible
Fees paidRenewal fee
29.08.2023Renewal fee patent year 03
29.08.2024Renewal fee patent year 04
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competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[X]JPH08130220  (NIPPON KOKAN KK) [X] 1,2,4-6,8-15 * abstract * * paragraph [0026] *;
 [X]US5585675  (KNOPF GEORGE S [US]) [X] 1,4,5,8-11,13 * abstract *;
 [X]US2006108680  (WU CHING-YUAN [TW], et al) [X] 1,4,13 * abstract *;
 [X]US2011260288  (SUKEKAWA MITSUNARI [JP], et al) [X] 1,2,4-6,8-15 * abstract * * paragraph [0081] *;
 [X]JP2011222796  (SEIKO EPSON CORP) [X] 1,4,5,8-11,13-15 * abstract *;
 [X]EP2426714  (FUJIKURA LTD [JP]) [X] 1,4,5,8-13 * abstract *;
 [A]US2014127910  (HIENO ATSUSHI [JP], et al) [A] 1-15 * abstract *;
 [X]US2016035738  (KAKEGAWA TOMOYASU [JP], et al) [X] 1-11,13-15 * abstract * * paragraph [0069] *;
 [X]US9613967  (CHIEN YI-HAO [TW], et al) [X] 1-15 * abstract * * column 3, line 54 - line 58 *;
 [A]WO2018231195  (INTEL CORP [US]) [A] 1-15 * abstract *;
 [A]WO2019190463  (INTEL CORP [US], et al) [A] 1-15* abstract *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.