-
EP3975263
European procedure
- EP About this file
- EP Legal status
- EP Federated register
- EP Event history
- EP Citations
- EP Patent family
- EP All documents
Extract from the Register of European Patents
EP About this file: EP3975263
| EP3975263 - METHODS FOR FORMING SEMICONDUCTOR DEVICES USING SACRIFICIAL CAPPING AND INSULATION LAYERS [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 24.02.2023 Database last updated on 14.09.2024 | |
| Former | The application has been published Status updated on 25.02.2022 | Most recent event Tooltip | 24.02.2023 | Application deemed to be withdrawn | published on 29.03.2023 [2023/13] | Applicant(s) | For all designated states NXP USA, Inc. 6501 William Cannon Drive West Austin TX 78735 / US | [2022/13] | Inventor(s) | 01 /
Huang, Jenn Hwa 5656 AG Eindhoven / NL | 02 /
Yue, Yuanzheng 5656 AG Eindhoven / NL | 03 /
Green, Bruce McRae 5656 AG Eindhoven / NL | 04 /
Moore, Karen Elizabeth Eindhoven, 5656 AG / GB | 05 /
Teplik, James Allen 5656 AG Eindhoven / NL | [2022/13] | Representative(s) | Miles, John Richard NXP SEMICONDUCTORS Intellectual Property Group Abbey House 25 Clarendon Road Redhill, Surrey RH1 1QZ / GB | [2022/13] | Application number, filing date | 21196348.3 | 13.09.2021 | [2022/13] | Priority number, date | US202017036681 | 29.09.2020 Original published format: US202017036681 | [2022/13] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP3975263 | Date: | 30.03.2022 | Language: | EN | [2022/13] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 24.02.2022 | Classification | IPC: | H01L29/778, H01L21/338, H01L21/265, // H01L29/08, H01L29/20 | [2022/13] | CPC: |
H01L29/7786 (EP,US);
H01L29/66462 (EP,US);
H01L21/26553 (EP,US);
H01L21/28575 (EP);
H01L29/0843 (EP,US);
H01L29/2003 (EP,US)
| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2022/13] | Extension states | BA | Not yet paid | ME | Not yet paid | Validation states | KH | Not yet paid | MA | Not yet paid | MD | Not yet paid | TN | Not yet paid | Title | German: | VERFAHREN ZUR HERSTELLUNG VON HALBLEITERBAUELEMENTEN UNTER VERWENDUNG VON OPFERABDECKUNGS- UND ISOLATIONSSCHICHTEN | [2022/13] | English: | METHODS FOR FORMING SEMICONDUCTOR DEVICES USING SACRIFICIAL CAPPING AND INSULATION LAYERS | [2022/13] | French: | PROCÉDÉS DE FORMATION DE DISPOSITIFS À SEMI-CONDUCTEURS À L'AIDE DE COUCHES DE RECOUVREMENT ET D'ISOLATION SACRIFICIELLES | [2022/13] | Examination procedure | 01.10.2022 | Application deemed to be withdrawn, date of legal effect [2023/13] | 11.11.2022 | Despatch of communication that the application is deemed to be withdrawn, reason: examination fee not paid in time [2023/13] |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XYI]US2019157440 (GREEN BRUCE MCRAE [US], et al) [X] 1,2,5,7-9,13 * figure 12 and associated text * [Y] 10-12 [I] 3,4,6,14,15; | [Y]JP2020088270 (TOYODA GOSEI KK) [Y] 10-12 * paragraphs [0020] , [0 26] , [0 27]; figures 4-6 ** abstract * |