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Extract from the Register of European Patents

EP About this file: EP4006955

EP4006955 - LOW-TEMPERATURE METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE ON AN INSULATOR [Right-click to bookmark this link]
StatusRequest for examination was made
Status updated on  29.04.2022
Database last updated on 25.09.2024
Most recent event   Tooltip24.11.2023New entry: Renewal fee paid 
Applicant(s)For all designated states
Commissariat à l'énergie atomique et aux énergies alternatives
Bâtiment le Ponant
25, Rue Leblanc
75015 Paris / FR
[N/P]
Former [2022/22]For all designated states
Commissariat à l'énergie atomique et aux énergies alternatives
Bâtiment le Ponant
25, rue Leblanc
75015 Paris / FR
Inventor(s)01 / REBOH, Shay
38054 GRENOBLE Cedex 09 / FR
02 / HARTMANN, Jean-Michel
38054 GRENOBLE Cedex 09 / FR
 [2022/22]
Representative(s)Brevalex
Tour Trinity
1 B Place de la Défense
92400 Courbevoie / FR
[N/P]
Former [2022/22]Brevalex
95, rue d'Amsterdam
75378 Paris Cedex 8 / FR
Application number, filing date21306639.225.11.2021
[2022/22]
Priority number, dateFR2020001225727.11.2020         Original published format: FR 2012257
[2022/22]
Filing languageFR
Procedural languageFR
PublicationType: A1 Application with search report 
No.:EP4006955
Date:01.06.2022
Language:FR
[2022/22]
Search report(s)(Supplementary) European search report - dispatched on:EP22.04.2022
ClassificationIPC:H01L21/20, H01L21/02, H01L21/762, H01L27/12
[2022/22]
CPC:
H01L21/02002 (EP); H01L21/76254 (US); H01L21/02532 (US);
H01L21/2007 (EP); H01L21/76256 (EP); H01L27/1203 (EP)
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2022/22]
Extension statesBANot yet paid
MENot yet paid
Validation statesKHNot yet paid
MANot yet paid
MDNot yet paid
TNNot yet paid
TitleGerman:NIEDRIGTEMPERATURVERFAHREN ZUR HERSTELLUNG EINES HALBLEITERSUBSTRATS AUF ISOLATOR[2022/22]
English:LOW-TEMPERATURE METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE ON AN INSULATOR[2022/22]
French:PROCÉDÉ BASSE TEMPÉRATURE DE FABRICATION D'UN SUBSTRAT SEMICONDUCTEUR SUR ISOLANT[2022/22]
Examination procedure25.11.2021Examination requested  [2022/22]
19.08.2022Amendment by applicant (claims and/or description)
19.08.2022Date on which the examining division has become responsible
Fees paidRenewal fee
23.11.2023Renewal fee patent year 03
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Documents cited:Search[IY]US6323108  (KUB FRANCIS J [US], et al) [I] 1-10 * columns 5-9; figure 1 * [Y] 11-15;
 [IA]CN101217107  (SHANGHAI SIMGUI TECHNOLOGY CO [CN]) [I] 1-10 * the whole document * [A] 11-15;
 [A]US2010003803  (OKA SATOSHI [JP], et al) [A] 1-15 * the whole document *;
 [A]FR2978605  (SOITEC SILICON ON INSULATOR [FR]) [A] 1-15* the whole document *;
 [YA]US9735062  (DORIS BRUCE B [US], et al) [Y] 11-15 * columns 3-8; figures 3-11 * [A] 1-10
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.