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Extract from the Register of European Patents

EP About this file: EP4174945

EP4174945 - SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR [Right-click to bookmark this link]
StatusRequest for examination was made
Status updated on  31.03.2023
Database last updated on 10.07.2024
FormerThe international publication has been made
Status updated on  07.01.2022
Most recent event   Tooltip28.05.2024The date on which the examining division becomes responsible, has been established 
28.05.2024Amendment by applicant 
Applicant(s)For all designated states
Sony Semiconductor Solutions Corporation
4-14-1 Asahi-cho
Atsugi-shi, Kanagawa 243-0014 / JP
[2023/18]
Inventor(s)01 / EJIRI, Hirokazu
Atsugi-shi, Kanagawa 243-0014 / JP
02 / OGI, Jun
Atsugi-shi, Kanagawa 243-0014 / JP
03 / KAWAHARA, Yuki
Atsugi-shi, Kanagawa 243-0014 / JP
04 / YAMANE, Chigusa
Atsugi-shi, Kanagawa 243-0014 / JP
 [2023/18]
Representative(s)MFG Patentanwälte Meyer-Wildhagen Meggle-Freund Gerhard PartG mbB
Amalienstraße 62
80799 München / DE
[2023/18]
Application number, filing date21834365.506.04.2021
[2023/18]
WO2021JP14607
Priority number, dateJP2020011208829.06.2020         Original published format: JP 2020112088
[2023/18]
Filing languageJA
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO2022004088
Date:06.01.2022
Language:JA
[2022/01]
Type: A1 Application with search report 
No.:EP4174945
Date:03.05.2023
Language:EN
[2023/18]
Search report(s)International search report - published on:JP06.01.2022
(Supplementary) European search report - dispatched on:EP01.12.2023
ClassificationIPC:H10N97/00, H01L23/522, H01L27/04, H01L21/822, H01L27/146, H01L31/10, H01L31/107
[2024/01]
CPC:
H01L27/14636 (EP,KR,US); H01L23/5228 (EP); H01L27/14627 (KR,US);
H01L27/14643 (KR); H01L27/14649 (EP); H01L27/14683 (US);
H01L28/20 (EP,KR); H01L28/24 (EP); H01L31/02027 (EP);
H01L31/022408 (EP); H01L31/107 (EP,KR,US); H01L23/5222 (EP);
H01L27/14634 (EP); H04N23/20 (EP) (-)
Former IPC [2023/18]H01L27/04, H01L21/822, H01L27/146, H01L31/10, H01L31/107, H04N5/369
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2023/18]
TitleGerman:HALBLEITERBAUELEMENT UND HERSTELLUNGSVERFAHREN DAFÜR[2023/18]
English:SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR[2023/18]
French:DISPOSITIF À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION[2023/18]
Entry into regional phase21.12.2022Translation filed 
19.01.2023National basic fee paid 
19.01.2023Search fee paid 
19.01.2023Designation fee(s) paid 
19.01.2023Examination fee paid 
Examination procedure19.01.2023Examination requested  [2023/18]
27.05.2024Amendment by applicant (claims and/or description)
28.05.2024Date on which the examining division has become responsible
Fees paidRenewal fee
20.04.2023Renewal fee patent year 03
15.03.2024Renewal fee patent year 04
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See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[XI]US2007235880  (YANG CHIN-SHENG [TW]) [X] 1-7,14,15 * paragraphs [0040] - [0073]; figure - * [I] 8-13;
 [XI]US2009302993  (FUJIWARA TSUYOSHI [JP], et al) [X] 1-3,14 * paragraphs [0049] - [0086]; figures 7M, 10L * [I] 8-13;
 [XI]US2019326423  (KOBAYASHI KUNIO [JP]) [X] 1-3,14 * paragraphs [0050] - [0063] - [0074] - [0080]; figures 4,7,11,12 *[I] 8-13
International search[AX]JP2009302082  (HITACHI LTD) [A] 4-11, 15-18, 20 [X] 1-3, 12-14, 19;
 [A]JP2018056558  (SEMICONDUCTOR ENERGY LAB CO LTD)[A] 1-20;
 [AX]JP2019192690  (FUJI ELECTRIC CO LTD) [A] 2-18, 20 [X] 1, 19
by applicantJP2009021509
 WO2018174090
 JP2018201005
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.