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EP4155835
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EP About this file: EP4155835
| EP4155835 - DIGITAL TIME CONVERTER AND PHASE LOCKING LOOP [Right-click to bookmark this link] | Status | Request for examination was made Status updated on 24.02.2023 Database last updated on 15.07.2024 | Most recent event Tooltip | 29.08.2023 | The date on which the examining division becomes responsible, has been established | 29.08.2023 | Amendment by applicant | Applicant(s) | For all designated states Commissariat à l'énergie atomique et aux énergies alternatives Bâtiment "Le Ponant D" 25 rue Leblanc 75015 Paris / FR | [2023/13] | Inventor(s) | 01 /
LACHARTRE, David 38054 GRENOBLE CEDEX 9 / FR | [2023/13] | Representative(s) | Cabinet Beaumont 4, Place Robert Schuman B.P. 1529 38025 Grenoble Cedex 1 / FR | [2023/13] | Application number, filing date | 22195766.5 | 15.09.2022 | [2023/13] | Priority number, date | FR20210010080 | 24.09.2021 Original published format: FR 2110080 | [2023/13] | Filing language | FR | Procedural language | FR | Publication | Type: | A1 Application with search report | No.: | EP4155835 | Date: | 29.03.2023 | Language: | FR | [2023/13] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 14.02.2023 | Classification | IPC: | G04F10/00, // H03M3/00 | [2023/13] | CPC: |
G04F10/005 (EP,US);
H03L7/093 (US);
H03L2207/50 (US);
H03M3/30 (EP);
H03M3/458 (US)
| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2023/13] | Extension states | BA | Not yet paid | ME | Not yet paid | Validation states | KH | Not yet paid | MA | Not yet paid | MD | Not yet paid | TN | Not yet paid | Title | German: | DIGITALER ZEITUMWANDLER UND PHASENREGELSCHLEIFE | [2023/13] | English: | DIGITAL TIME CONVERTER AND PHASE LOCKING LOOP | [2023/13] | French: | CONVERTISSEUR TEMPS NUMÉRIQUE ET BOUCLE À VERROUILLAGE DE PHASE | [2023/13] | Examination procedure | 15.09.2022 | Examination requested [2023/13] | 29.08.2023 | Amendment by applicant (claims and/or description) | 29.08.2023 | Date on which the examining division has become responsible |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XI]US2017194972 (SAI AKIHIDE [JP], et al) [X] 1-4,6,10,11 * paragraph [0088]; figures 2,7,8 * [I] 5,7-9,12,13; | [X] - DAYANIK MEHMET BATUHAN ET AL, "A 28.5-33.5GHz fractional-N PLL using a 3rd order noise shaping time-to-digital converter with 176fs resolution", 2013 PROCEEDINGS OF THE ESSCIRC (ESSCIRC), IEEE, doi:10.1109/ESSCIRC.2015.7313906, ISSN 1930-8833, ISBN 978-1-4799-0643-7, (20150914), pages 376 - 379, (20151030), XP032803411 [X] 1 * Section II;; figure 1 * DOI: http://dx.doi.org/10.1109/ESSCIRC.2015.7313906 | [A] - WANG ZIXUAN ET AL, "An ADPLL with a MASH 1-1-1 [Delta][Sigma] Time-digital c", MELECON 2014 - 2014 17TH IEEE MEDITERRANEAN ELECTROTECHNICAL CONFERENCE, IEEE, (20140413), doi:10.1109/MELCON.2014.6820544, pages 266 - 270, XP032597874 [A] 1-13 * Section II;; figures 3-5 * DOI: http://dx.doi.org/10.1109/MELCON.2014.6820544 | [A] - YING CAO ET AL, "1-1-1 MASH $\Delta \Sigma$ Time-to-Digital Converters With 6 ps Resolution and Third-Order Noise-Shaping", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, (20120901), vol. 47, no. 9, doi:10.1109/JSSC.2012.2199530, ISSN 0018-9200, pages 2093 - 2106, XP011457913 [A] 1-13 * Section II;; figures 2-4 * DOI: http://dx.doi.org/10.1109/JSSC.2012.2199530 | [A] - REZVANYVARDOM M. ET AL, "A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification", RADIOENGINEERING., CZ, vol. 24, no. 3, doi:10.13164/re.2015.0800, ISSN 1210-2512, (20150915), pages 800 - 807, URL: https://www.radioeng.cz/fulltexts/2015/15_03_0800_0807.pdf, XP093019826 [A] 1-13 * Section 3;; figures 1-8 * DOI: http://dx.doi.org/10.13164/re.2015.0800 |