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EP4167144
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EP About this file: EP4167144
| EP4167144 - METHOD FOR DESIGNING AN OPTIMIZED HARDWARE ARCHITECTURE FOR THE EXECUTION OF A NEURAL NETWORK [Right-click to bookmark this link] | Status | Request for examination was made Status updated on 17.03.2023 Database last updated on 11.09.2024 | Most recent event Tooltip | 02.08.2023 | The date on which the examining division becomes responsible, has been established | 02.08.2023 | Amendment by applicant | Applicant(s) | For all designated states Commissariat à l'énergie atomique et aux énergies alternatives Bâtiment "Le Ponant D" 25 rue Leblanc 75015 Paris / FR | For all designated states Universite De Bretagne Sud 27 rue Armand Guillemot 56100 Lorient / FR | [2023/16] | Inventor(s) | 01 /
ALI, Nermine 91191 GIF-SUR-YVETTE Cedex / FR | 02 /
PHILIPPE, Jean-Marc 91190 GIF-SUR-YVETTE / FR | 03 /
TAIN, Benoît 91191 GIF-SUR-YVETTE Cedex / FR | 04 /
COUSSY, Philippe 56270 PLOEMEUR / FR | [2023/16] | Representative(s) | Atout PI Laplace Immeuble Up On 25 Boulevard Romain Rolland CS 40072 75685 Paris Cedex 14 / FR | [N/P] |
| Former [2023/16] | Atout PI Laplace Immeuble "Visium" 22, avenue Aristide Briand 94117 Arcueil Cedex / FR | Application number, filing date | 22199722.4 | 05.10.2022 | [2023/16] | Priority number, date | FR20210010880 | 14.10.2021 Original published format: FR 2110880 | [2023/16] | Filing language | FR | Procedural language | FR | Publication | Type: | A1 Application with search report | No.: | EP4167144 | Date: | 19.04.2023 | Language: | FR | [2023/16] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 05.01.2023 | Classification | IPC: | G06N3/063, G06F30/30, G06N3/12, G06N3/10, // G06N3/04, G06N3/08 | [2023/16] | CPC: |
G06N3/063 (EP);
G06F30/323 (EP);
G06N3/0464 (EP);
G06N3/105 (EP);
G06N3/126 (EP);
G06N3/086 (EP)
| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, ME, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2023/16] | Extension states | BA | Not yet paid | Validation states | KH | Not yet paid | MA | Not yet paid | MD | Not yet paid | TN | Not yet paid | Title | German: | VERFAHREN ZUM ENTWURF EINER OPTIMIERTEN HARDWAREARCHITEKTUR ZUR AUSFÜHRUNG EINES NEURONALEN NETZWERKS | [2023/16] | English: | METHOD FOR DESIGNING AN OPTIMIZED HARDWARE ARCHITECTURE FOR THE EXECUTION OF A NEURAL NETWORK | [2023/16] | French: | METHODE DE CONCEPTION D'UNE ARCHITECTURE MATERIELLE OPTIMISEE POUR L'EXECUTION D'UN RESEAU DE NEURONES | [2023/16] | Examination procedure | 05.10.2022 | Examination requested [2023/16] | 02.08.2023 | Amendment by applicant (claims and/or description) | 02.08.2023 | Date on which the examining division has become responsible |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [I] - SHAHSHAHANI MASOUD ET AL, "A Framework for Modeling, Optimizing, and Implementing DNNs on FPGA Using HLS", 2020 IEEE 14TH DALLAS CIRCUITS AND SYSTEMS CONFERENCE (DCAS), IEEE, (20201115), doi:10.1109/DCAS51144.2020.9330667, pages 1 - 6, XP033886892 [I] 1-8 * Sections II.A, II.C;; figure 1 * DOI: http://dx.doi.org/10.1109/DCAS51144.2020.9330667 | [A] - SHAHSHAHANI MASOUD ET AL, "Resource and Performance Estimation for CNN Models using Machine Learning", 2021 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), IEEE, (20210707), doi:10.1109/ISVLSI51109.2021.00019, pages 43 - 48, XP033963451 [A] 1-8 * Section III. See references [7] and [13].;; figure 1 * DOI: http://dx.doi.org/10.1109/ISVLSI51109.2021.00019 | [A] - SHAHSHAHANI MASOUD ET AL, "An Automated Tool for Implementing Deep Neural Networks on FPGA", 2021 34TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2021 20TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID), IEEE, (20210220), doi:10.1109/VLSID51830.2021.00060, pages 322 - 327, XP033906396 [A] 1-8 * Section III. See reference [5].;; figure 1 * DOI: http://dx.doi.org/10.1109/VLSID51830.2021.00060 | [A] - ATEFEH SOHRABIZADEH ET AL, "AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators", ARXIV.ORG, CORNELL UNIVERSITY LIBRARY, 201 OLIN LIBRARY CORNELL UNIVERSITY ITHACA, NY 14853, (20210831), XP091022572 [A] 1-8 * Sections 2, 3.2, 4, 5, 7;; table 2 * | [A] - GUYUE HUANG ET AL, "Machine Learning for Electronic Design Automation: A Survey", ARXIV.ORG, CORNELL UNIVERSITY LIBRARY, 201 OLIN LIBRARY CORNELL UNIVERSITY ITHACA, NY 14853, (20210308), XP081902405 [A] 1-8 * Section 3 * | [A] - ALI NERMINE ET AL, "Deep Neural Networks Characterization Framework for Efficient Implementation on Embedded Systems", 2020 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), IEEE, doi:10.1109/SIPS50750.2020.9195227, ISSN 2374-7390, ISBN 978-1-7281-8099-1, (20201020), pages 1 - 6, (20200911), XP033852082 [A] 1-8 * figures 2,4 * DOI: http://dx.doi.org/10.1109/SiPS50750.2020.9195227 | by applicant | - VENKATESAN, R.SHAO, Y. S.WANG, M.CLEMONS, J.DAI, S.FOJTIK, M.KHAILANY, B., "Magnet: A modular accelerator generator for neural networks", In 2019 IEEE/ACM International Conférence on Computer-Aided Design (ICCAD), (20191100), pages 1 - 8, XP033678199 | - NANE, R.SIMA, V. M.PILATO, C.CHOI, J.FORT, B.CANIS, A.BERTELS, K., "A survey and evaluation of FPGA high-level synthesis tools", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (20150000), vol. 35, no. 10, doi:10.1109/TCAD.2015.2513673, pages 1591 - 1604, XP011622420 DOI: http://dx.doi.org/10.1109/TCAD.2015.2513673 |