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EP4297075
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EP About this file: EP4297075
| EP4297075 - MOBILITY IMPROVEMENT IN GATE ALL AROUND TRANSISTORS BASED ON SUBSTRATE ORIENTATION [Right-click to bookmark this link] | Status | Request for examination was made Status updated on 07.06.2024 Database last updated on 07.06.2024 | |
| Former | The application has been published Status updated on 24.11.2023 | Most recent event Tooltip | 07.06.2024 | The date on which the examining division becomes responsible, has been established | 07.06.2024 | Request for examination filed | published on 10.07.2024 [2024/28] | 07.06.2024 | Change - designated states | published on 10.07.2024 [2024/28] | Applicant(s) | For all designated states INTEL Corporation 2200 Mission College Blvd. Santa Clara, CA 95054 / US | [2023/52] | Inventor(s) | 01 /
KAVALIEROS, Jack Portland, 97229 / US | 02 /
RADOSAVLJEVIC, Marko Portland, 97229 / US | 03 /
GLASS, Glenn Portland, 97229 / US | 04 /
BUDREVICH, Aaron Portland, 97229 / US | 05 /
AGRAWAL, Ashish Hillsboro, 97124 / US | 06 /
SUNG, Seung Hoon Portland, 97229 / US | 07 /
BOWONDER, Anupama Portland, 97229 / US | 08 /
PAUL, Rajat Portland, 97229 / US | 09 /
GUHA, Biswajeet Hillsboro, 97124 / US | 10 /
NAHM, Rambert Beavertown, 97006 / US | 11 /
MERRILL, Devin McMinnville, 97128 / US | 12 /
ONI, Adedapo North Plains, 97133 / US | 13 /
HSU, William Portland, 97229 / US | 14 /
GHOSE, Susmita Hillsboro, 97124 / US | 15 /
SUBRAMANIAN, Shruti Hillsboro, 97124 / US | 16 /
BRIGGS, Natalie Hillsboro, 97124 / US | 17 /
RAMAMURTHY, Rahul Hillsboro, 97123 / US | 18 /
TSENG, Hsin-Ying Hillsboro, 97006 / US | [2023/52] | Representative(s) | HGF HGF Limited 1 City Walk Leeds LS11 9DX / GB | [2023/52] | Application number, filing date | 23170147.5 | 26.04.2023 | [2023/52] | Priority number, date | US202217847555 | 23.06.2022 Original published format: US202217847555 | [2023/52] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP4297075 | Date: | 27.12.2023 | Language: | EN | [2023/52] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 27.11.2023 | Classification | IPC: | H01L21/8238, H01L27/092, H01L29/04, H01L29/775 | [2023/52] | CPC: |
H01L27/092 (EP);
H01L29/78696 (EP,US);
B82Y10/00 (EP);
H01L21/823807 (EP);
H01L29/045 (EP);
H01L29/0673 (EP,US);
H01L29/42392 (EP,US);
H01L29/66439 (EP);
H01L29/775 (EP);
H01L21/823878 (EP)
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| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, ME, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2024/28] |
| Former [2023/52] | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, ME, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR | Extension states | BA | Not yet paid | Validation states | KH | Not yet paid | MA | Not yet paid | MD | Not yet paid | TN | Not yet paid | Title | German: | MOBILITÄTSVERBESSERUNG BEI GATE-ALL-AROUND-TRANSISTOREN DURCH SUBSTRATAUSRICHTUNG | [2023/52] | English: | MOBILITY IMPROVEMENT IN GATE ALL AROUND TRANSISTORS BASED ON SUBSTRATE ORIENTATION | [2023/52] | French: | AMÉLIORATION DE LA MOBILITÉ DANS DES TRANSISTORS À GRILLE ENVELOPPANTE BASÉE SUR L'ORIENTATION DU SUBSTRAT | [2023/52] | Examination procedure | 03.06.2024 | Amendment by applicant (claims and/or description) | 03.06.2024 | Examination requested [2024/28] | 03.06.2024 | Date on which the examining division has become responsible |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XY]US2014209855 (CEA STEPHEN M [US], et al) [X] 1-4,6-12 * paragraphs [0026] , [0 30] - [0032] - [0 35] , [0 41] - [0044] - [0 47] , [0 50] - [0067]; figures 1A, 3, 6, 7 * [Y] 5; | [XYI]US2018286764 (RODDER MARK S [US], et al) [X] 1-4,6,7,10-12 * paragraphs [0052] , [0 53] , [0 55] - [0065]; figure 2 * [Y] 5 [I] 9; | [XYI]WO2021203899 (INST OF MICROELECTRONICS CAS [CN]) [X] 1-4,6-8,10-12 * page 4, line 1 - line 15 * * page 11, line 1 - line 3; figure 7 * * page 16, line 9 - page 17, line 2; figure 19 * * page 19, line 14 - line 29; figures 23(b), 24, 27(a) * [Y] 5 [I] 9; | [Y] - WECKX P ET AL, "Novel forksheet device architecture as ultimate logic scaling device towards 2nm", 2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), IEEE, (20191207), doi:10.1109/IEDM19573.2019.8993635, XP033714586 [Y] 5 * abstract * DOI: http://dx.doi.org/10.1109/IEDM19573.2019.8993635 |