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EP0020116
European procedure
Extract from the Register of European Patents
EP About this file: EP0020116
| EP0020116 - Masterslice semiconductor device and method of producing it [Right-click to bookmark this link] | |||
| Former [1980/25] | Semiconductor device | ||
| [1984/11] | Status | No opposition filed within time limit Status updated on 24.01.1985 Database last updated on 19.10.2024 | Most recent event Tooltip | 24.01.1985 | No opposition filed within time limit | published on 27.03.1985 [1985/13] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | [N/P] |
| Former [1980/25] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | Inventor(s) | 01 /
Ohno, Kenichi 25-12, Kamiikedai 5-chome Ohta-ku Tokyo 145 / JP | 02 /
Ogawa, Rokutaro 40-4, Fujigaoka 2-chome Midori-ku Yokohama-shi Kanagawa 227 / JP | 03 /
Hosomizu, Tohru 33-18, Hiranuma 1-chome Nishi-ku Yokohama-shi Kanagawa 220 / JP | [1980/25] | Representative(s) | Abbott, Leonard Charles, et al GILL JENNINGS & EVERY 53-64 Chancery Lane London WC2A 1HN / GB | [1980/25] | Application number, filing date | 80301734.2 | 23.05.1980 | [1980/25] | Priority number, date | JP19790063203 | 24.05.1979 Original published format: JP 6320379 | JP19790063965 | 25.05.1979 Original published format: JP 6396579 | [1980/25] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0020116 | Date: | 10.12.1980 | Language: | EN | [1980/25] | Type: | B1 Patent specification | No.: | EP0020116 | Date: | 14.03.1984 | Language: | EN | [1984/11] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 23.09.1980 | Classification | IPC: | H01L27/02, H01L23/52 | [1980/25] | CPC: |
H01L23/525 (EP,US);
H01L27/11801 (EP,US);
H01L2924/0002 (EP,US)
| C-Set: |
H01L2924/0002, H01L2924/00 (EP,US)
| Designated contracting states | DE, FR, GB, NL [1980/25] | Title | German: | Halbleitervorrichtung vom "MASTERSLICE"-Typ und Herstellungsverfahren | [1984/11] | English: | Masterslice semiconductor device and method of producing it | [1984/11] | French: | Dispositif semiconducteur du type "MASTERSLICE" et procédé de fabrication | [1984/11] |
| Former [1980/25] | Halbleitervorrichtung | ||
| Former [1980/25] | Semiconductor device | ||
| Former [1980/25] | Dispositif semiconducteur | File destroyed: | 03.03.2001 | Examination procedure | 09.06.1980 | Examination requested [1980/25] | 19.10.1981 | Despatch of a communication from the examining division (Time limit: M06) | 17.04.1982 | Reply to a communication from the examining division | 09.06.1982 | Despatch of a communication from the examining division (Time limit: M06) | 09.12.1982 | Reply to a communication from the examining division | 07.06.1983 | Despatch of communication of intention to grant (Approval: ) | 25.08.1983 | Communication of intention to grant the patent | 20.09.1983 | Fee for grant paid | 20.09.1983 | Fee for publishing/printing paid | Opposition(s) | 15.12.1984 | No opposition filed within time limit [1985/13] | Fees paid | Renewal fee | 14.05.1982 | Renewal fee patent year 03 | 31.05.1983 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | FR2374817 [ ] (NIPPON TELEGRAPH & TELEPHONE [JP]); | US3618201 [ ] (MAKIMOTO TSUGIO, et al); | US3999214 [ ] (CASS EUGENE E) | [ ] - ELECTRONICS & COMMUNICATIONS IN JAPAN, Vol. 55-C, November 1972, Tokyo JP TAKAHIRO OKABE et al.: "A design approach for LSI using chip selection and circuit modification techniques", pages 78-85 * Page 78, summary; page 78, column 2, paragraph 2 - page 80, column 2, paragraph 2; page 81, column 2, paragraph 2 - page 83, column 2, paragraph 2; figures 4-7, 10-12 * | [ ] - REVIEW OF THE ELECTRICAL COMMUNICATIONS LABORATORIES, Vol. 26, September-October 1978, Tokyo JP K. WADA & K. TAKEDA: "Master-slice layout design for emitter coupled logic LSI", pages 1355-1366. * Page 1355, Abstract; page 1355, column 2, paragraph 2 - page 1364, column 2, paragraph 2; figures 1-7, 10-14 * | [ ] - IBM TECHNICAL DISCLOSURE BULLETIN Vol. 19, December 1976, New York US Y.K. PURI: "PLA layout including second-level metallization shorting bar", pages 2630-2631 * Pages 2630-2631 * |