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EP0025261
European procedure
Extract from the Register of European Patents
EP About this file: EP0025261
| EP0025261 - A method of manufacturing a semiconductor device [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 13.04.1984 Database last updated on 14.09.2024 | Most recent event Tooltip | 13.04.1984 | No opposition filed within time limit | published on 13.06.1984 [1984/24] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | [N/P] |
| Former [1981/11] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | Inventor(s) | 01 /
Kurahashi, Toshio 925-A-403, Mamedo-cho Kohoku-ku Yokohama-shi Kanagawa, 222 / JP | 02 /
Tokitomo, Kazuo 260-12, Kitatakizawa Hachiman Itsukimachi Aizuwakamatsu-shi Fukushima, 965 / JP | 03 /
Kiriseko, Tadashi 3-6-16, Wakabadai Shiroyama-cho Tsukiu-gun Kanagawa, 220-01 / JP | [1981/11] | Representative(s) | Bedggood, Guy Stuart, et al Haseltine Lake & Co., Imperial House, 15-19 Kingsway London WC2B 6UD / GB | [N/P] |
| Former [1981/11] | Bedggood, Guy Stuart, et al Haseltine Lake & Co. Hazlitt House 28 Southampton Buildings Chancery Lane London WC2A 1AT / GB | Application number, filing date | 80302337.3 | 10.07.1980 | [1981/11] | Priority number, date | JP19790097655 | 31.07.1979 Original published format: JP 9765579 | [1981/11] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0025261 | Date: | 18.03.1981 | Language: | EN | [1981/11] | Type: | B1 Patent specification | No.: | EP0025261 | Date: | 15.06.1983 | Language: | EN | [1983/24] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 08.01.1981 | Classification | IPC: | H01L21/31 | [1981/11] | CPC: |
H01L21/02282 (EP,US);
H01L21/02129 (EP,US);
H01L21/02164 (EP,US);
H01L21/0272 (EP,US);
H01L21/306 (EP,US);
H01L21/316 (US);
H01L21/76819 (EP,US);
H01L21/7688 (EP,US);
H01L23/5329 (EP,US);
| C-Set: |
H01L2924/0002, H01L2924/00 (EP,US)
| Designated contracting states | DE, FR, GB, NL [1981/16] |
| Former [1981/11] | AT, BE, CH, DE, FR, GB, IT, LI, LU, NL, SE | Title | German: | Verfahren zur Herstellung einer Halbleitervorrichtung | [1981/11] | English: | A method of manufacturing a semiconductor device | [1981/11] | French: | Procédé de fabrication d'un dispositif à semiconducteur | [1981/11] | File destroyed: | 20.04.2002 | Examination procedure | 11.11.1980 | Despatch of communication of loss of particular rights: designated state(s) AT, BE, CH, IT, LU, SE | 25.01.1981 | Loss of particular rights, legal effect: designated state(s) | 05.08.1981 | Examination requested [1981/41] | 23.12.1981 | Despatch of a communication from the examining division (Time limit: M04) | 23.04.1982 | Reply to a communication from the examining division | 26.08.1982 | Despatch of communication of intention to grant (Approval: ) | 18.11.1982 | Communication of intention to grant the patent | 07.02.1983 | Fee for grant paid | 07.02.1983 | Fee for publishing/printing paid | Opposition(s) | 16.03.1984 | No opposition filed within time limit [1984/24] | Fees paid | Renewal fee | 01.07.1982 | Renewal fee patent year 03 | Penalty fee | Penalty fee Rule 85a EPC 1973 | 11.08.1980 | AT M02 Not yet paid | 11.08.1980 | BE M02 Not yet paid | 11.08.1980 | CH M02 Not yet paid | 11.08.1980 | IT M02 Not yet paid | 11.08.1980 | LI M02 Not yet paid | 11.08.1980 | LU M02 Not yet paid | 11.08.1980 | SE M02 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]FR2188304 (COMMISSARIAT ENERGIE ATOMIQUE [FR]); | [A]GB1523677 (TOKYO SHIBAURA ELECTRIC CO); | [A]US4029562 (FENG BAI-CWO, et al); | [A]US3723277 (SCHMIEDECKE W) | Examination | - Patents Abstracts of Japan Vol. 2, No. 124, 18-10-78, p. 7230E78 and the corresponding JPA 53-93366 |