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EP0031995
European procedure
Extract from the Register of European Patents
EP About this file: EP0031995
| EP0031995 - Semiconductor RAM device comprising a matrix of static memory cells [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 12.01.1987 Database last updated on 13.07.2024 | Most recent event Tooltip | 12.01.1987 | No opposition filed within time limit | published on 04.03.1987 [1987/10] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | [N/P] |
| Former [1981/28] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | Inventor(s) | 01 /
Kurafuji, Setsuo 2-5, Edakita 2-chome Midori-ku Yokohama-shi Kanagawa 227 / JP | [1981/28] | Representative(s) | Abbott, Leonard Charles, et al GILL JENNINGS & EVERY 53-64 Chancery Lane London WC2A 1HN / GB | [1981/28] | Application number, filing date | 80304189.6 | 21.11.1980 | [1981/28] | Priority number, date | JP19790154578 | 29.11.1979 Original published format: JP 15457879 | [1981/28] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0031995 | Date: | 15.07.1981 | Language: | EN | [1981/28] | Type: | A3 Search report | No.: | EP0031995 | Date: | 17.11.1982 | Language: | EN | [1982/46] | Type: | B1 Patent specification | No.: | EP0031995 | Date: | 26.02.1986 | Language: | EN | [1986/09] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 16.09.1982 | Classification | IPC: | G11C7/00, G11C11/40 | [1981/28] | CPC: |
G11C11/419 (EP,US);
G11C11/412 (EP,US)
| Designated contracting states | DE, FR, GB, NL [1981/28] | Title | German: | Halbleiterspeicheranordnung mit matrixartig angeordneten statischen Speicherzellen | [1981/28] | English: | Semiconductor RAM device comprising a matrix of static memory cells | [1981/28] | French: | Dispositif de mémoire à semi-conducteurs comprenant une matrice de cellules de mémoire statiques | [1981/28] | Examination procedure | 02.12.1980 | Examination requested [1981/28] | 13.04.1984 | Despatch of a communication from the examining division (Time limit: M04) | 02.08.1984 | Reply to a communication from the examining division | 20.02.1985 | Despatch of communication of intention to grant (Approval: ) | 22.05.1985 | Communication of intention to grant the patent | 02.08.1985 | Fee for grant paid | 02.08.1985 | Fee for publishing/printing paid | Opposition(s) | 27.11.1986 | No opposition filed within time limit [1987/10] | Fees paid | Renewal fee | 19.11.1982 | Renewal fee patent year 03 | 03.11.1983 | Renewal fee patent year 04 | 12.11.1984 | Renewal fee patent year 05 | 09.11.1985 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]US3879621 (CAVALIERE JOSEPH RICHARD, et al) | [X] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 13, no. 6, November 1970, pages 1720-1722, New York, USA, D.L. CRITCHLOW: 'Sense amplifier for igfet memory' | [Y] - ELECTRONICS, vol. 52, no. 20, 27th September 1979, pages 131-139, New York, USA, D. HUFFMAN: 'Polysilicon-load microprocessors' | [Y] - IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. SC-11, no. 5, October 1976, pages 602-609, New York, USA, J.M. SCHLAGETER et al.: 'Two 4k static 5-v ram's' | [A] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 16, no. 9, February 1974, pages 2792-2793, New York, USA, A. FURMAN et al.: 'Sense latch circuit for memory cells' |