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EP0040377
European procedure
Extract from the Register of European Patents
EP About this file: EP0040377
| EP0040377 - Integrated circuit device for writing and reading information [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 30.06.1987 Database last updated on 12.07.2024 | Most recent event Tooltip | 30.06.1987 | No opposition filed within time limit | published on 19.08.1987 [1987/34] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho, Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [1981/47] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP | Inventor(s) | 01 /
Wada, Masashi 2-8-2, Shiomidai Isogo-ku Yokohama-shi / JP | [1981/47] | Representative(s) | Blumbach Weser Bergen Kramer Zwirner Hoffmann Patentanwälte Radeckestrasse 43 81245 München / DE | [N/P] |
| Former [1981/47] | Blumbach Weser Bergen Kramer Zwirner Hoffmann Patentanwälte Radeckestrasse 43 D-81245 München / DE | Application number, filing date | 81103540.1 | 08.05.1981 | [1981/47] | Priority number, date | JP19800066245 | 19.05.1980 Original published format: JP 6624580 | [1981/47] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0040377 | Date: | 25.11.1981 | Language: | EN | [1981/47] | Type: | A3 Search report | No.: | EP0040377 | Date: | 26.10.1983 | Language: | EN | [1983/43] | Type: | B1 Patent specification | No.: | EP0040377 | Date: | 03.09.1986 | Language: | EN | [1986/36] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 25.08.1983 | Classification | IPC: | H01L27/08, G11C11/34 | [1981/47] | CPC: |
G11C16/0416 (EP,US);
H01L27/0921 (EP,US);
H01L27/105 (US)
| Designated contracting states | DE, FR, GB [1986/36] |
| Former [1981/47] | DE, FR, GB, NL | Title | German: | Integrierte Schaltung zum Lesen und Schreiben von Informationen | [1981/47] | English: | Integrated circuit device for writing and reading information | [1981/47] | French: | Circuit intégré pour l'écriture et la lecture d'informations | [1981/47] | Examination procedure | 23.12.1983 | Examination requested [1984/11] | 20.12.1984 | Despatch of a communication from the examining division (Time limit: M04) | 20.04.1985 | Reply to a communication from the examining division | 30.09.1985 | Despatch of communication of intention to grant (Approval: ) | 23.01.1986 | Communication of intention to grant the patent | 17.04.1986 | Fee for grant paid | 17.04.1986 | Fee for publishing/printing paid | Opposition(s) | 04.06.1987 | No opposition filed within time limit [1987/34] | Fees paid | Renewal fee | 17.05.1983 | Renewal fee patent year 03 | 17.05.1984 | Renewal fee patent year 04 | 11.05.1985 | Renewal fee patent year 05 | 14.05.1986 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]JP55015222 ; | [A]US3971001 (LODI ROBERT J) | [Y] - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, 5th-7th December 1977, pages 291-293, Washington D.C., USA, S. FUKUNAGA et al.: "FA-CMOS process for low power PROM with low avalanche injection voltage" | [Y] - RCA TECHNICAL NOTES, no. 876, 12th February 1971, pages 1-4, Princeton, N.J., USA, W.J. DENNEHY: "Non-latching integrated circuits" | [A] - PATENTS ABSTRACTS OF JAPAN, vol. 4, no. 44(E-5)(526), 5th April 1980, page 78E5 & JP - A - 55 015 222 (MITSUBISHI) 02-02-1980, & JP55015222 A 00000000 |