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EP0033198
European procedure
Extract from the Register of European Patents
EP About this file: EP0033198
| EP0033198 - Bias circuit for a field effect transistor [Right-click to bookmark this link] | |||
| Former [1981/31] | Input optimized FET bias circuit | ||
| [1984/13] | Status | No opposition filed within time limit Status updated on 06.02.1985 Database last updated on 26.06.2024 | Most recent event Tooltip | 06.02.1985 | No opposition filed within time limit | published on 10.04.1985 [1985/15] | Applicant(s) | For all designated states FORD AEROSPACE & COMMUNICATIONS CORPORATION 300 Renaissance Center P.O. Box 43339 Detroit, Michigan 48243 / US | [1981/31] | Inventor(s) | 01 /
Rubin, Michael David 12716 Larchmont Avenue Saratoga California 95070 / US | 02 /
Ho, Pang Ting 3371 Brower Avenue Mountain View California 94040 / US | [1981/31] | Representative(s) | Crawford, Andrew Birkby, et al A.A. Thornton & Co. 235 High Holborn London WC1V 7LE / GB | [N/P] |
| Former [1981/31] | Crawford, Andrew Birkby, et al A.A. THORNTON & CO. Northumberland House 303-306 High Holborn London WC1V 7LE / GB | Application number, filing date | 81300113.8 | 12.01.1981 | [1981/31] | Priority number, date | US19800116527 | 29.01.1980 Original published format: US 116527 | [1981/31] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0033198 | Date: | 05.08.1981 | Language: | EN | [1981/31] | Type: | B1 Patent specification | No.: | EP0033198 | Date: | 28.03.1984 | Language: | EN | [1984/13] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 14.05.1981 | Classification | IPC: | H03F3/21, H03F1/56 | [1981/31] | CPC: |
H03F1/301 (EP,US);
H03F1/0261 (EP,US);
H03G3/30 (EP,US);
H03F2200/18 (EP,US)
| Designated contracting states | DE, FR, GB [1981/31] | Title | German: | Vorspannungsschaltung für einen Feldeffekttransistor | [1984/13] | English: | Bias circuit for a field effect transistor | [1984/13] | French: | Circuit de polarisation pour un transistor à effet de champ | [1984/13] |
| Former [1981/31] | FET-Vorspannschaltung mit optimiertem Eingang | ||
| Former [1981/31] | Input optimized FET bias circuit | ||
| Former [1981/31] | Circuit de polarisation pour FET à entrée optimalisée | Examination procedure | 19.10.1981 | Examination requested [1981/52] | 13.08.1982 | Despatch of a communication from the examining division (Time limit: M04) | 18.12.1982 | Reply to a communication from the examining division | 18.04.1983 | Despatch of communication of intention to grant (Approval: ) | 12.07.1983 | Communication of intention to grant the patent | 15.09.1983 | Fee for grant paid | 15.09.1983 | Fee for publishing/printing paid | Opposition(s) | 29.12.1984 | No opposition filed within time limit [1985/15] | Fees paid | Renewal fee | 22.12.1982 | Renewal fee patent year 03 | 17.12.1983 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | US4011518 [ ] (IRVINE JAMES A, et al) | Examination | US3984783 | US3996524 |