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Extract from the Register of European Patents

EP About this file: EP0055558

EP0055558 - Method of manufacturing a semiconductor device [Right-click to bookmark this link]
Former [1982/27]Semiconductor device
[1986/32]
StatusNo opposition filed within time limit
Status updated on  03.06.1987
Database last updated on 22.08.2024
Most recent event   Tooltip09.07.1988Lapse of the patent in a contracting statepublished on 24.08.1988 [1988/34]
Applicant(s)For all designated states
FUJITSU LIMITED
1015, Kamikodanaka, Nakahara-ku Kawasaki-shi
Kanagawa 211 / JP
[N/P]
Former [1982/27]For all designated states
FUJITSU LIMITED
1015, Kamikodanaka, Nakahara-ku
Kawasaki-shi, Kanagawa 211 / JP
Inventor(s)01 / Toyokura, Nobuo
1569-1, Shinsaku Takatsu-ku Kawasaki-shi
Kanagawa 213 / JP
02 / Taguchi, Masao
4-3-4-201, Araisono Sagamihara-shi
Kanagawa 228 / JP
[1982/27]
Representative(s)Sunderland, James Harry, et al
Haseltine Lake LLP Lincoln House 300 High Holborn London
WC1V 7JH / GB
[N/P]
Former [1982/27]Sunderland, James Harry, et al
HASELTINE LAKE & CO Hazlitt House 28 Southampton Buildings Chancery Lane
London WC2A 1AT / GB
Application number, filing date81305941.718.12.1981
[1982/27]
Priority number, dateJP1980018905629.12.1980         Original published format: JP 18905680
[1982/27]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0055558
Date:07.07.1982
Language:EN
[1982/27]
Type: A3 Search report 
No.:EP0055558
Date:05.10.1983
Language:EN
[1983/40]
Type: B1 Patent specification 
No.:EP0055558
Date:06.08.1986
Language:EN
[1986/32]
Search report(s)(Supplementary) European search report - dispatched on:EP02.08.1983
ClassificationIPC:H01L21/225, H01L29/94, H01L27/10, H01L21/314, // G11C11/24
[1982/27]
CPC:
H01L21/02183 (EP,US); H01L21/02181 (EP,US); H01L21/02186 (EP,US);
H01L21/02189 (EP,US); H01L21/2254 (EP,US); H01L21/2255 (EP,US);
H01L21/28185 (EP,US); H01L21/28229 (EP,US); H01L21/31683 (US);
H01L21/3185 (US); H01L27/04 (EP,US); H01L29/517 (EP,US);
H01L29/94 (EP,US); H10B12/03 (EP,US); H10B12/30 (EP,US);
H01L21/0217 (EP,US); H01L21/022 (EP,US) (-)
Designated contracting statesDE,   FR,   GB,   NL [1982/27]
TitleGerman:Verfahren zur Herstellung einer Halbleiteranordnung[1986/32]
English:Method of manufacturing a semiconductor device[1986/32]
French:Méthode de fabrication d'un dispositif semiconducteur[1986/32]
Former [1982/27]Halbleiteranordnung
Former [1982/27]Semiconductor device
Former [1982/27]Dispositif semiconducteur
File destroyed:12.06.1999
Examination procedure09.11.1983Examination requested  [1984/03]
17.08.1984Despatch of a communication from the examining division (Time limit: M05)
24.01.1985Reply to a communication from the examining division
20.03.1985Despatch of a communication from the examining division (Time limit: M01)
16.04.1985Reply to a communication from the examining division
14.10.1985Despatch of communication of intention to grant (Approval: )
30.01.1986Communication of intention to grant the patent
20.02.1986Fee for grant paid
20.02.1986Fee for publishing/printing paid
Opposition(s)07.05.1987No opposition filed within time limit [1987/30]
Fees paidRenewal fee
12.12.1983Renewal fee patent year 03
14.12.1984Renewal fee patent year 04
11.12.1985Renewal fee patent year 05
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipNL06.08.1986
[1988/34]
Documents cited:Search[Y]JP55065458  ;
 [Y]JP52113181  ;
 [A]DE2555187  (SIEMENS AG);
 [X]US4112575  (FU HORNG-SEN, et al)
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.