-
EP0055161
European procedure
Extract from the Register of European Patents
EP About this file: EP0055161
| EP0055161 - Multilayer metal silicide interconnections for integrated circuits [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 07.07.1986 Database last updated on 28.06.2024 | Most recent event Tooltip | 07.03.1997 | Lapse of the patent in a contracting state | published on 23.04.1997 [1997/17] | Applicant(s) | For all designated states FAIRCHILD CAMERA & INSTRUMENT CORPORATION 464 Ellis Street Mountain View California 94042 / US | [N/P] |
| Former [1982/26] | For all designated states FAIRCHILD CAMERA & INSTRUMENT CORPORATION 464 Ellis Street Mountain View California 94042 / US | Inventor(s) | 01 /
Lehrer, William I. 1161 Seena Avenue Los Altos California 94022 / US | [1982/26] | Representative(s) | Chareyron, Lucien, et al Service Brevets Patent Department Etudes et Productions Schlumberger BP 202 92142 Clamart Cédex / FR | [N/P] |
| Former [1985/04] | Chareyron, Lucien, et al Service Brevets Patent Department Etudes et Productions Schlumberger BP 202 F-92142 Clamart Cédex / FR | ||
| Former [1982/26] | Chareyron, Lucien Schlumberger Limited Service Brevets c/o Giers 12, place des Etats Unis B.P. 121 F-92124 Montrouge Cédex / FR | Application number, filing date | 81401940.2 | 07.12.1981 | [1982/26] | Priority number, date | US19800214615 | 09.12.1980 Original published format: US 214615 | [1982/26] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0055161 | Date: | 30.06.1982 | Language: | EN | [1982/26] | Type: | B1 Patent specification | No.: | EP0055161 | Date: | 04.09.1985 | Language: | EN | [1985/36] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 19.05.1982 | Classification | IPC: | H01L21/90, H01L23/52 | [1982/26] | CPC: |
H01L21/76838 (EP,US);
H01L21/76889 (EP,US);
H01L23/5226 (EP,US);
H01L23/53257 (EP,US);
H01L2924/0002 (EP,US)
| C-Set: |
H01L2924/0002, H01L2924/00 (EP,US)
| Designated contracting states | CH, DE, FR, GB, IT, LI, NL [1982/26] | Title | German: | Mehrschichtige Metallsilizid-Verbindungsleiter für integrierte Schaltungen | [1982/26] | English: | Multilayer metal silicide interconnections for integrated circuits | [1982/26] | French: | Interconnexions multicouches à siliciure métallique pour circuits intégrés | [1982/26] | Examination procedure | 09.12.1982 | Examination requested [1983/08] | 05.01.1984 | Despatch of a communication from the examining division (Time limit: M06) | 22.06.1984 | Reply to a communication from the examining division | 08.11.1984 | Despatch of communication of intention to grant (Approval: ) | 05.02.1985 | Communication of intention to grant the patent | 22.04.1985 | Fee for grant paid | 22.04.1985 | Fee for publishing/printing paid | Opposition(s) | 05.06.1986 | No opposition filed within time limit [1986/35] | Fees paid | Renewal fee | 21.11.1983 | Renewal fee patent year 03 | 22.11.1984 | Renewal fee patent year 04 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]FR2445625 (WESTERN ELECTRIC CO [US]); | [Y]US4152823 (HALL JOHN H) | [A] - IBM Technical Disclosure Bulletin, Vol. 22, No. 12, May 1980, New York, US B.L. CROWDER et al.: "Improved Conductivity Polysilicon Lines for MOSFET and Bipolar Technology" pages 5466-5467 | Examination | EP0002165 | EP0017697 |