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Extract from the Register of European Patents

EP About this file: EP0073487

EP0073487 - Method for manufacturing three-dimensional semiconductor device [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  25.05.1989
Database last updated on 19.07.2024
Most recent event   Tooltip28.09.2007Lapse of the patent in a contracting statepublished on 31.10.2007  [2007/44]
Applicant(s)For all designated states
Kabushiki Kaisha Toshiba
72, Horikawa-cho, Saiwai-ku Kawasaki-shi
Kanagawa-ken 210-8572 / JP
[N/P]
Former [1983/10]For all designated states
KABUSHIKI KAISHA TOSHIBA
72, Horikawa-cho, Saiwai-ku
Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP
Inventor(s)01 / Inoue, Tomoyasu
2-2-8-504, Atago
Tama-shi Tokyo / JP
02 / Shibata, Kenji
575 Kamiharama Nakahara-ku
Kawasaki-shi / JP
[1983/10]
Representative(s)Lehn, Werner, et al
Hoffmann Eitle, Patent- und Rechtsanwälte, Postfach 81 04 20
81904 München / DE
[N/P]
Former [1983/10]Lehn, Werner, Dipl.-Ing., et al
Hoffmann, Eitle & Partner, Patentanwälte, Postfach 81 04 20
D-81904 München / DE
Application number, filing date82107859.926.08.1982
[1983/10]
Priority number, dateJP1981013542131.08.1981         Original published format: JP 13542181
JP1981013542231.08.1981         Original published format: JP 13542281
[1983/10]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0073487
Date:09.03.1983
Language:EN
[1983/10]
Type: A3 Search report 
No.:EP0073487
Date:03.04.1985
Language:EN
[1985/14]
Type: B1 Patent specification 
No.:EP0073487
Date:20.07.1988
Language:EN
[1988/29]
Search report(s)(Supplementary) European search report - dispatched on:EP28.01.1985
ClassificationIPC:H01L27/06
[1983/10]
CPC:
H01L21/02488 (EP,US); H01L21/02381 (EP,US); H01L21/02532 (EP,US);
H01L21/02598 (EP,US); H01L21/02675 (US); H01L21/02689 (EP,US);
H01L21/02691 (EP,US); H01L21/743 (EP,US); H01L21/8221 (EP,US);
H01L23/5283 (EP,US); H01L27/0688 (EP,US); H01L29/78618 (EP,US);
H01L29/78654 (EP,US); H01L2924/0002 (EP,US) (-)
C-Set:
H01L2924/0002, H01L2924/00 (EP,US)
Designated contracting statesDE,   FR,   GB,   IT [1983/10]
TitleGerman:Verfahren zur Herstellung einer dreidimensionalen Halbleitervorrichtung[1983/10]
English:Method for manufacturing three-dimensional semiconductor device[1983/10]
French:Procédé de fabrication d'un dispositif semi-conducteur tri-dimensionnel[1983/10]
Examination procedure26.08.1982Examination requested  [1983/10]
26.08.1986Despatch of a communication from the examining division (Time limit: M06)
20.02.1987Reply to a communication from the examining division
14.10.1987Despatch of communication of intention to grant (Approval: Yes)
13.01.1988Communication of intention to grant the patent
29.03.1988Fee for grant paid
29.03.1988Fee for publishing/printing paid
Opposition(s)21.04.1989No opposition filed within time limit [1989/28]
Fees paidRenewal fee
30.08.1984Renewal fee patent year 03
13.08.1985Renewal fee patent year 04
14.08.1986Renewal fee patent year 05
12.08.1987Renewal fee patent year 06
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipIT20.07.1988
[2007/44]
Former [1999/42]IT20.07.1988
Documents cited:Search[X]DE3043913  (HITACHI LTD [JP]);
 [A]US4272880  (PASHLEY RICHARD D);
 [A]GB2064866  (GEN ELECTRIC CO LTD)
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.