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EP0074541
European procedure
Extract from the Register of European Patents
EP About this file: EP0074541
| EP0074541 - Method for the production of a semiconductor device comprising dielectrically isolating regions [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 08.01.1990 Database last updated on 27.07.2024 | Most recent event Tooltip | 08.01.1990 | No opposition filed within time limit | published on 28.02.1990 [1990/09] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | [N/P] |
| Former [1983/12] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | Inventor(s) | 01 /
Ogawa, Tetsuya Fujinodai-danchi 1-17-207, 3486 Honmachida Machida-shi Tokyo 194 / JP | 02 /
Toyokura, Nobuo 1569-1, Shinsaku Takatsu-ku Kawasaki-shi Kanagawa 213 / JP | [1983/12] | Representative(s) | Sajda, Wolf E., et al Meissner Bolte Patentanwälte Rechtsanwälte Partnerschaft mbB Widenmayerstrasse 47 80538 München / DE | [N/P] |
| Former [1988/42] | Sajda, Wolf E., Dipl.-Phys., et al MEISSNER, BOLTE & PARTNER Widenmayerstrasse 48 D-80538 München / DE | ||
| Former [1988/40] | Sajda, Wolf E., Dipl.-Phys. MEISSNER, BOLTE & PARTNER Widenmayerstrasse 48 D-80538 München / DE | ||
| Former [1986/27] | Reinländer & Bernhardt Patentanwälte Postfach 86 06 24 D-8000 München 86 / DE | ||
| Former [1983/12] | Reinländer & Bernhardt Patentanwälte Orthstrasse 12 D-8000 München 60 / DE | Application number, filing date | 82107889.6 | 27.08.1982 | [1983/12] | Priority number, date | JP19810142911 | 10.09.1981 Original published format: JP 14291181 | [1983/12] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0074541 | Date: | 23.03.1983 | Language: | EN | [1983/12] | Type: | A3 Search report | No.: | EP0074541 | Date: | 30.05.1984 | Language: | EN | [1984/22] | Type: | B1 Patent specification | No.: | EP0074541 | Date: | 01.03.1989 | Language: | EN | [1989/09] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 30.03.1984 | Classification | IPC: | H01L21/76, H01L21/324, H01L21/90 | [1983/12] | CPC: |
H01L21/28512 (EP,US);
H01L21/3245 (EP,US);
H01L21/743 (EP,US);
H01L21/76 (EP,US);
H01L21/76224 (EP,US);
H01L21/76801 (EP,US);
H01L21/76829 (EP,US)
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| Designated contracting states | DE, FR, GB [1983/12] | Title | German: | Verfahren zur Herstellung einer Halbleiteranordnung mit dielektrischen Isolationszonen | [1989/09] | English: | Method for the production of a semiconductor device comprising dielectrically isolating regions | [1983/12] | French: | Procédé pour la production d'un dispositif semi-conducteur comportant des régions d'isolation diélectriques | [1983/12] |
| Former [1983/12] | Verfahren zur Herstellung einer Halbleiteranordnung mit dielektrischen Isolationsmassen | File destroyed: | 15.01.2000 | Examination procedure | 30.04.1984 | Examination requested [1984/28] | 03.05.1985 | Despatch of a communication from the examining division (Time limit: M08) | 13.01.1986 | Reply to a communication from the examining division | 18.08.1986 | Despatch of a communication from the examining division (Time limit: M08) | 24.04.1987 | Reply to a communication from the examining division | 06.07.1988 | Despatch of communication of intention to grant (Approval: No) | 19.08.1988 | Despatch of communication of intention to grant (Approval: later approval) | 29.08.1988 | Communication of intention to grant the patent | 12.09.1988 | Fee for grant paid | 12.09.1988 | Fee for publishing/printing paid | Opposition(s) | 01.12.1989 | No opposition filed within time limit [1990/09] | Fees paid | Renewal fee | 30.08.1984 | Renewal fee patent year 03 | 29.08.1985 | Renewal fee patent year 04 | 14.08.1986 | Renewal fee patent year 05 | 06.10.1987 | Renewal fee patent year 06 | 29.08.1988 | Renewal fee patent year 07 | Penalty fee | Additional fee for renewal fee | 31.08.1987 | 06 M06 Fee paid on 06.10.1987 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]US4069577 (DINGWALL ANDREW GORDON FRANCIS); | [X]US4181537 (ICHINOHE EISUKE [JP]); | [X]US4282647 (RICHMAN PAUL); | [XP]DE3023410 (SIEMENS AG [DE]) | [X] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 23, no. 8, January 1981 New York, US D.W. ORMOND: "Method of manufacturing dielectrically isolated regions of silicon utilizing high pressure steam", pages 3694-3697 | [X] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 21, no. 7, December 1978 New York, US H.B. POGGE: "Single mask selfaligned trench isolation/diffusion process", pages 2734-2735 |