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Extract from the Register of European Patents

EP About this file: EP0078480

EP0078480 - Method for fusing and connecting solder of IC chip [Right-click to bookmark this link]
StatusThe application has been refused
Status updated on  02.07.1986
Database last updated on 20.07.2024
Most recent event   Tooltip15.08.2008Change - representativepublished on 17.09.2008  [2008/38]
Applicant(s)For all designated states
Hitachi, Ltd.
5-1, Marunouchi 1-chome
Chiyoda-ku
Tokyo 100 / JP
[N/P]
Former [1983/19]For all designated states
Hitachi, Ltd.
5-1, Marunouchi 1-chome
Chiyoda-ku, Tokyo 100 / JP
Inventor(s)01 / Ohshima, Muneo Hitachi Hachimanyama
Apartment No. 113, 1545 Yoshida-cho Totsuka-ku
Yokohama-shi Kanagawa-ken / JP
02 / Kenmotsu, Akihiro
866-15, Kameino
Fujisawa-shi Kanagawa-ken / JP
[1983/19]
Representative(s)Beetz & Partner mbB
Patentanwälte
Prinzregentenstraße 54
80538 München / DE
[N/P]
Former [2008/38]Beetz & Partner
Patentanwälte Steinsdorfstrasse 10
80538 München / DE
Former [1983/19]Patentanwälte Beetz - Timpe - Siegfried Schmitt-Fumian - Mayr
Steinsdorfstrasse 10
D-80538 München / DE
Application number, filing date82109845.625.10.1982
[1983/19]
Priority number, dateJP1981017141128.10.1981         Original published format: JP 17141181
[1983/19]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0078480
Date:11.05.1983
Language:EN
[1983/19]
Type: A3 Search report 
No.:EP0078480
Date:25.07.1984
Language:EN
[1984/30]
Search report(s)(Supplementary) European search report - dispatched on:EP25.05.1984
ClassificationIPC:H01L21/60, H01L23/48
[1983/19]
CPC:
H01L24/10 (EP); H01L24/13 (EP); H01L24/81 (EP);
H05K3/3436 (EP); H01L2224/13 (EP); H01L2224/13099 (EP);
H01L2224/13111 (EP); H01L2224/14505 (EP); H01L2224/16 (EP);
H01L2224/81136 (EP); H01L2224/81801 (EP); H01L2924/01005 (EP);
H01L2924/01006 (EP); H01L2924/01014 (EP); H01L2924/01015 (EP);
H01L2924/01033 (EP); H01L2924/0105 (EP); H01L2924/01078 (EP);
H01L2924/01082 (EP); H01L2924/014 (EP); H01L2924/14 (EP);
H05K2201/094 (EP); H05K2201/09781 (EP); H05K2201/2036 (EP);
H05K3/3463 (EP); Y02P70/50 (EP) (-)
C-Set:
H01L2224/13, H01L2924/00 (EP)
Designated contracting statesDE,   FR [1983/19]
TitleGerman:Verfahren zum Schmelzen und Verbinden des Lots eines integrierten Schaltungschips[1983/19]
English:Method for fusing and connecting solder of IC chip[1983/19]
French:Procédé pour fondre et lier de la brasure d'une puce à circuit intégré[1983/19]
File destroyed:03.12.1992
Examination procedure30.07.1984Examination requested  [1984/41]
11.09.1985Despatch of a communication from the examining division (Time limit: M04)
07.01.1986Reply to a communication from the examining division
21.02.1986Despatch of communication that the application is refused, reason: substantive examination [1986/34]
03.03.1986Application refused, date of legal effect [1986/34]
Fees paidRenewal fee
29.10.1984Renewal fee patent year 03
30.10.1985Renewal fee patent year 04
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Documents cited:Search[A]JP56111234  ;
 [Y]GB2062963  (HITACHI LTD)
 [Y]  - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 14, no. 1, June 1971, pages 257-258, New York, US; R.L. HAMILTON et al.: "Thermal stress resistant solder reflow chip joints".
 [A]  - SOLID STATE TECHNOLOGY, vol. 12, no. 9, September 1969, pages 33-41, part 2, New York, US; L.F. MILLER: "A survey of chip joining techniques".
 [A]  - PATENTS ABSTRACTS OF JAPAN, vol. 5, no. 186 (E-84)[858], 25th November 1981 & JP-A-56 111 234 (HITACHI SEISAKUSHO K.K.) 02-09-1981, & JP56111234 A 00000000
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.