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EP0085767
European procedure
Extract from the Register of European Patents
EP About this file: EP0085767
| EP0085767 - Voltage level responsive circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 19.05.1989 Database last updated on 21.08.2024 | Most recent event Tooltip | 19.05.1989 | No opposition filed within time limit | published on 05.07.1989 [1989/27] | Applicant(s) | For all designated states International Business Machines Corporation New Orchard Road Armonk, NY 10504 / US | [N/P] |
| Former [1983/33] | For all designated states International Business Machines Corporation Old Orchard Road Armonk, N.Y. 10504 / US | Inventor(s) | 01 /
Lam, Chung Hon 23 Hillside Drive Williston Vermont 05495 / US | 02 /
Peterson, Charles William 37 Greenfield Road Essex Junction Vermont 05452 / US | [1983/33] | Representative(s) | Mönig, Anton IBM Deutschland Informationssysteme GmbH, Patentwesen und Urheberrecht 70548 Stuttgart / DE | [N/P] |
| Former [1985/15] | Mönig, Anton, Dipl.-Ing. IBM Deutschland Informationssysteme GmbH, Patentwesen und Urheberrecht D-70548 Stuttgart / DE | ||
| Former [1983/33] | Busch, Robert, Dipl.-Ing. Schönaicher Strasse 220 D-7030 Böblingen / DE | Application number, filing date | 82111113.5 | 02.12.1982 | [1983/33] | Priority number, date | US19820346431 | 05.02.1982 Original published format: US 346431 | [1983/33] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0085767 | Date: | 17.08.1983 | Language: | EN | [1983/33] | Type: | A3 Search report | No.: | EP0085767 | Date: | 08.01.1986 | Language: | EN | [1986/02] | Type: | B1 Patent specification | No.: | EP0085767 | Date: | 20.07.1988 | Language: | EN | [1988/29] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 07.11.1985 | Classification | IPC: | G11C17/00 | [1983/33] | CPC: |
G11C17/12 (EP,US)
| Designated contracting states | DE, FR, GB [1983/33] | Title | German: | Spannungspegelempfindliche Schaltung | [1983/33] | English: | Voltage level responsive circuit | [1983/33] | French: | Circuit sensible à un niveau de tension | [1983/33] | File destroyed: | 03.03.2001 | Examination procedure | 15.12.1983 | Examination requested [1984/08] | 17.02.1987 | Despatch of a communication from the examining division (Time limit: M04) | 10.06.1987 | Reply to a communication from the examining division | 11.11.1987 | Despatch of communication of intention to grant (Approval: Yes) | 19.01.1988 | Communication of intention to grant the patent | 29.01.1988 | Fee for grant paid | 29.01.1988 | Fee for publishing/printing paid | Opposition(s) | 21.04.1989 | No opposition filed within time limit [1989/27] | Fees paid | Renewal fee | 11.12.1984 | Renewal fee patent year 03 | 13.12.1985 | Renewal fee patent year 04 | 12.12.1986 | Renewal fee patent year 05 | 11.12.1987 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]EP0015070 (FUJITSU LTD [JP]); | [YD]US4242604 (SMITH FREDERICK J [US]); | [XP]EP0052010 (FUJITSU LTD [JP]) | [Y] - IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. ED-26, no. 4, April 1976, pages 560-563, IEEE, New York, US; K. NATORI et al.: "A 64 kbit MOS dynamic random access memory" | [A] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 23, no. 11, April 1981, pages 4856-4857, New York, US; J.E. SELLECK et al.: "Accessing circuitry and method for a read-only memory system" |