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EP0069534
European procedure
Extract from the Register of European Patents
EP About this file: EP0069534
| EP0069534 - Superconducting logic circuit [Right-click to bookmark this link] | |||
| Former [1983/02] | Superconducting logic circuit and superconducting switching device therefor | ||
| [1987/03] | Status | No opposition filed within time limit Status updated on 20.11.1987 Database last updated on 08.04.2026 | Most recent event Tooltip | 31.07.2009 | Change - representative | published on 02.09.2009 [2009/36] | Applicant(s) | For all designated states Hitachi, Ltd. 5-1, Marunouchi 1-chome Chiyoda-ku Tokyo 100 / JP | [N/P] |
| Former [1983/02] | For all designated states Hitachi, Ltd. 5-1, Marunouchi 1-chome Chiyoda-ku, Tokyo 100 / JP | Inventor(s) | 01 /
Kotera, Nobuo 2-18-3-301, Minami-cho Kokubunji-shi Tokyo / JP | 02 /
Hatano, Juji 4-1-2, Hiyoshi-cho Kokubunji-shi Tokyo / JP | 03 /
Asano, Atsushi 1-47-3-F302, Akatsuki-cho Hachioji-shi Tokyo / JP | 04 /
Kawabe, Ushio 1-8-46, Sakae-cho Hamuramachi Nishitama-gun Tokyo / JP | [1983/02] | Representative(s) | Calderbank, Thomas Roger, et al Mewburn Ellis LLP City Tower 40 Basinghall Street London EC2V 5DE / GB | [N/P] |
| Former [2009/36] | Calderbank, Thomas Roger, et al Mewburn Ellis LLP 33 Gutter Lane London EC2V 8AS / GB | ||
| Former [1983/02] | Calderbank, Thomas Roger, et al MEWBURN ELLIS York House 23 Kingsway London WC2B 6HP / GB | Application number, filing date | 82303428.5 | 30.06.1982 | [1983/02] | Priority number, date | JP19810101221 | 01.07.1981 Original published format: JP 10122181 | [1983/02] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0069534 | Date: | 12.01.1983 | Language: | EN | [1983/02] | Type: | A3 Search report | No.: | EP0069534 | Date: | 31.08.1983 | Language: | EN | [1983/35] | Type: | B1 Patent specification | No.: | EP0069534 | Date: | 14.01.1987 | Language: | EN | [1987/03] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 28.06.1983 | Classification | IPC: | H03K19/195, H03K17/92 | [1983/02] | CPC: |
H03K19/1956 (EP,US);
H03K17/92 (EP,US);
Y10S505/858 (EP,US);
Y10S505/861 (EP,US)
| Designated contracting states | DE, FR, GB, NL [1983/02] | Title | German: | Supra-leitende-logische Schaltung | [1987/03] | English: | Superconducting logic circuit | [1987/03] | French: | Circuit logique supra-conducteur | [1987/03] |
| Former [1983/02] | Supra-leitende-logische Schaltung und supra-leitende Schaltvorrichtung dafür | ||
| Former [1983/02] | Superconducting logic circuit and superconducting switching device therefor | ||
| Former [1983/02] | Circuit logique supra-conducteur et dispositif de commutation supra-conducteur pour celui-ci | Examination procedure | 13.08.1982 | Examination requested [1983/02] | 28.12.1984 | Despatch of a communication from the examining division (Time limit: M06) | 04.07.1985 | Reply to a communication from the examining division | 04.04.1986 | Despatch of communication of intention to grant (Approval: ) | 17.07.1986 | Communication of intention to grant the patent | 15.08.1986 | Fee for grant paid | 15.08.1986 | Fee for publishing/printing paid | Opposition(s) | 15.10.1987 | No opposition filed within time limit [1988/01] | Fees paid | Renewal fee | 20.06.1984 | Renewal fee patent year 03 | 19.06.1985 | Renewal fee patent year 04 | 20.06.1986 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A] IBM TECHNICAL DISCLOSURE BULLETIN, vol. 24, no. 1B, June 1981, pages 736-737, New York, USA [A] | [A] JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 19, suppl. 19-1, 1980, pages 607-611, Tokyo, JP. [A] |