Extract from the Register of European Patents

EP About this file: EP0073149

EP0073149 - Semiconductor chip mounting module [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  21.09.1988
Database last updated on 11.04.2026
Most recent event   Tooltip21.09.1988No opposition filed within time limitpublished on 09.11.1988 [1988/45]
Applicant(s)For all designated states
SPERRY CORPORATION
1290, Avenue of the Americas
New York, N.Y. 10019 / US
[1983/09]
Inventor(s)01 / Currie, Thomas Peter
198 Montrofe Place
St. Paul, Minnesota 55104 / US
02 / Goldberg, Norman, Dr.
1580 Tralee Drive
Dresher, Pa. 19025 / US
[1983/09]
Representative(s)Orchard, Oliver John
JOHN ORCHARD & CO. Staple Inn Buildings North High Holborn
London WC1V 7PZ / GB
[N/P]
Former [1984/19]Orchard, Oliver John
JOHN ORCHARD & CO. Staple Inn Buildings North High Holborn
London WC1V 7PZ / GB
Former [1983/09]Michaels, Peter Albert
Sperry Univac Patent & Licensing Services M.S. N1W4 Sperry Rand Ltd. Sperry Univac Centre Brentfields
London NW10 8LS / GB
Application number, filing date82304406.020.08.1982
[1983/09]
Priority number, dateUS1981029410021.08.1981         Original published format: US 294100
[1983/09]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0073149
Date:02.03.1983
Language:EN
[1983/09]
Type: A3 Search report 
No.:EP0073149
Date:19.12.1984
Language:EN
[1984/51]
Type: B1 Patent specification 
No.:EP0073149
Date:25.11.1987
Language:EN
[1987/48]
Search report(s)(Supplementary) European search report - dispatched on:EP17.10.1984
ClassificationIPC:H01L23/52
[1983/09]
CPC:
H10W76/153 (EP,US); H10W70/685 (EP,US); H10W70/611 (EP,US);
H10W72/075 (EP,US); H10W72/29 (EP,US); H10W72/5363 (EP,US);
H10W72/952 (EP,US); H10W90/724 (EP,US); H10W90/754 (EP,US) (-)
Designated contracting statesDE,   FR,   GB,   IT [1983/09]
TitleGerman:Halbleiterchip-Montierungsmodul[1983/09]
English:Semiconductor chip mounting module[1983/09]
French:Module de montage pour puce semi-conductrice[1983/09]
Examination procedure30.11.1984Examination requested  [1985/08]
10.04.1986Despatch of a communication from the examining division (Time limit: M04)
20.08.1986Reply to a communication from the examining division
18.02.1987Despatch of communication of intention to grant (Approval: )
27.05.1987Communication of intention to grant the patent
24.08.1987Fee for grant paid
24.08.1987Fee for publishing/printing paid
Opposition(s)26.08.1988No opposition filed within time limit [1988/45]
Fees paidRenewal fee
13.08.1984Renewal fee patent year 03
01.08.1985Renewal fee patent year 04
18.08.1986Renewal fee patent year 05
19.06.1987Renewal fee patent year 06
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Documents cited:Search[AP] JP56120147  
 [Y]   IBM TECHNICAL DISCLOSURE BULLETIN, vol. 23, no. 9, February 1981, pages 4062-4063, New York, US; S.M. JENSEN et al.: "Pin/chip carrier assembly" [Y]
 [A]   IBM TECHNICAL DISCLOSURE BULLETIN, vol. 23, no. 3, August 1980, page 966, New York, US; P.F. IAFRATE et al.: "Integrated circuit wafer package" [A]
 [A]   IBM TECHNICAL DISCLOSURE BULLETIN, vol. 22, no. 3, August 1979, pages 948-949, New York, US; L.R. CUTTING et al.: "Stacked MC module with variable size substrates" [A]
 [A]   IBM TECHNICAL DISCLOSURE BULLETIN, vol. 20, no. 6, November 1977, pages 2221-2222, New York, US; J.A. BENENATI: "Semiconductor module" [A]
 [AP]   PATENTS ABSTRACTS OF JAPAN, vol. 5, no. 198 (E-87)[870], 16th December 1981; & JP - A - 56 120 147 (HITACHI SEISAKUSHO K.K.) 21-09-1981 [AP]
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