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EP0096225
European procedure
Extract from the Register of European Patents
EP About this file: EP0096225
| EP0096225 - Interlaced programmable logic array having shared elements [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 14.06.1989 Database last updated on 02.09.2024 | Most recent event Tooltip | 14.06.1989 | No opposition filed within time limit | published on 02.08.1989 [1989/31] | Applicant(s) | For all designated states International Business Machines Corporation New Orchard Road Armonk, NY 10504 / US | [N/P] |
| Former [1983/51] | For all designated states International Business Machines Corporation Old Orchard Road Armonk, N.Y. 10504 / US | Inventor(s) | 01 /
Kalter, Howard Leo 14 Village Drive Colchester, VT 05446 / US | 02 /
Wiedman, Francis Walter Route 100 Stowe, VT 05672 / US | [1983/51] | Representative(s) | Möhlen, Wolfgang IBM Corporation Säumerstrasse 4 8803 Rüschlikon / CH | [N/P] |
| Former [1983/51] | Möhlen, Wolfgang C., Dipl.-Ing. IBM Corporation Säumerstrasse 4 CH-8803 Rüschlikon / CH | Application number, filing date | 83104486.2 | 06.05.1983 | [1983/51] | Priority number, date | US19820387132 | 10.06.1982 Original published format: US 387132 | [1983/51] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0096225 | Date: | 21.12.1983 | Language: | EN | [1983/51] | Type: | A3 Search report | No.: | EP0096225 | Date: | 20.03.1985 | Language: | EN | [1985/12] | Type: | B1 Patent specification | No.: | EP0096225 | Date: | 10.08.1988 | Language: | EN | [1988/32] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 15.01.1985 | Classification | IPC: | H03K19/177, G06F7/50 | [1985/04] | CPC: |
G06F7/5057 (EP,US);
H03K19/096 (EP,US);
H03K19/1772 (EP,US)
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| Former IPC [1983/51] | H03K19/177 | Designated contracting states | DE, FR, GB [1983/51] | Title | German: | Verschlungene programmierbare logische Anordnung mit geteilten Elementen | [1983/51] | English: | Interlaced programmable logic array having shared elements | [1983/51] | French: | Réseau logique programmable entrelacé comportant des éléments partagés | [1983/51] | File destroyed: | 20.04.2002 | Examination procedure | 26.04.1984 | Examination requested [1984/28] | 27.10.1986 | Despatch of a communication from the examining division (Time limit: M04) | 05.02.1987 | Reply to a communication from the examining division | 21.07.1987 | Despatch of communication of intention to grant (Approval: ) | 10.11.1987 | Communication of intention to grant the patent | 15.12.1987 | Fee for grant paid | 15.12.1987 | Fee for publishing/printing paid | Opposition(s) | 11.05.1989 | No opposition filed within time limit [1989/31] | Fees paid | Renewal fee | 24.05.1985 | Renewal fee patent year 03 | 23.05.1986 | Renewal fee patent year 04 | 29.05.1987 | Renewal fee patent year 05 | 31.05.1988 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [AD]US3890603 (JONES JOHN W, et al); | [YD]US3974366 (HEBENSTREIT ERNST); | [AD]US4140967 (BALASUBRAMANIAN PERUVEMBA S, et al); | [A]GB2011669 (IBM) | [Y] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 24, no. 8, January 1982, pages 4291-4292, New York, US; H.O. ASKIN et al.: "PLA with intermixed AND and OR arrays" | [A] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 24, no. 6, November 1981, pages 2971-2973, New York, US; P.E. ALLARD et al.: "Variable multifold programmable logic array" | [XP] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 25, no. 7A, December 1982, pages 3502-3504, New York, US; H.N. KOTECHA: "Merged programmable logic array using two-bit read-only storage device" | [A] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 20, no. 2, July 1977, page 672, New York, US; W.W. WU: "Pin sharing in a PLA code" |