-
EP0097379
European procedure
Extract from the Register of European Patents
EP About this file: EP0097379
| EP0097379 - Method for manufacturing semiconductor devices [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 16.02.1991 Database last updated on 09.04.2026 | Most recent event Tooltip | 16.02.1991 | No opposition filed within time limit | published on 10.04.1991 [1991/15] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [1984/01] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP | Inventor(s) | 01 /
Iwasaki, Hiroshi 47-11, Kagawa Chigasaki-shi Kanagawa-ken / JP | [1984/01] | Representative(s) | Lehn, Werner, et al Hoffmann Eitle, Patent- und Rechtsanwälte, Postfach 81 04 20 81904 München / DE | [N/P] |
| Former [1984/01] | Lehn, Werner, Dipl.-Ing., et al Hoffmann, Eitle & Partner, Patentanwälte, Postfach 81 04 20 D-81904 München / DE | Application number, filing date | 83106162.7 | 23.06.1983 | [1984/01] | Priority number, date | JP19820108069 | 23.06.1982 Original published format: JP 10806982 | [1984/01] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0097379 | Date: | 04.01.1984 | Language: | EN | [1984/01] | Type: | A3 Search report | No.: | EP0097379 | Date: | 08.10.1986 | Language: | EN | [1986/41] | Type: | B1 Patent specification | No.: | EP0097379 | Date: | 25.04.1990 | Language: | EN | [1990/17] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 22.08.1986 | Classification | IPC: | H01L21/82, H01L27/06, H01L27/13 | [1984/01] | CPC: |
H10D84/0109 (EP,US);
H10D84/038 (EP,US);
H10D84/401 (EP,US)
| Designated contracting states | DE, FR, GB, NL [1984/01] | Title | German: | Verfahren zum Herstellen von Halbleiteranordnungen | [1984/01] | English: | Method for manufacturing semiconductor devices | [1984/01] | French: | Procédé de fabrication de dispositifs semi-conducteurs | [1984/01] | Examination procedure | 23.06.1983 | Examination requested [1984/01] | 28.04.1988 | Despatch of a communication from the examining division (Time limit: M04) | 29.08.1988 | Reply to a communication from the examining division | 14.12.1988 | Despatch of communication of intention to grant (Approval: No) | 22.05.1989 | Despatch of a communication from the examining division (Time limit: M04) | 22.09.1989 | Reply to a communication from the examining division | 28.09.1989 | Despatch of communication of intention to grant (Approval: later approval) | 17.10.1989 | Communication of intention to grant the patent | 09.01.1990 | Fee for grant paid | 09.01.1990 | Fee for publishing/printing paid | Opposition(s) | 26.01.1991 | No opposition filed within time limit [1991/15] | Fees paid | Renewal fee | 20.06.1985 | Renewal fee patent year 03 | 11.06.1986 | Renewal fee patent year 04 | 22.06.1987 | Renewal fee patent year 05 | 14.06.1988 | Renewal fee patent year 06 | 12.06.1989 | Renewal fee patent year 07 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A] IBM TECHNICAL DISCLOSURE BULLETIN, vol. 16, no. 8, January 1974, pages 2701-2703, New York, US; I. ANTIPOV: "Forming complementary field-effect devices and NPN transistors" [A] | Examination | IBM Technical Disclosure Bulletin, vol. 16, no. 8, January 1974, pp. 2719-2720 [A] |