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EP0089221
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EP About this file: EP0089221
| EP0089221 - Electrographic method of forming conductive circuit patterns and circuit boards formed thereby [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 21.02.1986 Database last updated on 17.07.2024 | Most recent event Tooltip | 15.08.2008 | Change - applicant | published on 17.09.2008 [2008/38] | Applicant(s) | For all designated states Eastman Kodak Company 343 State Street Rochester, NY 14650-2201 / US | [N/P] |
| Former [2008/38] | For all designated states Eastman Kodak Company 343 State Street Rochester NY 14650-2201 / US | ||
| Former [1983/38] | For all designated states EASTMAN KODAK COMPANY (a New Jersey corporation) 343 State Street Rochester, New York 14650 / US | Inventor(s) | 01 /
Kan, Hsin-Chia 28 Bent Oak Trail Fairport New York 14450 / US | 02 /
McCabe, John Murray 6 Cavan Way Pittsford New York 14534 / US | [1983/38] | Representative(s) | Pepper, John Herbert, et al KODAK LIMITED Patent Department P.O. Box 114 190 High Holborn London WC1V 7EA / GB | [1983/38] | Application number, filing date | 83301403.8 | 15.03.1983 | [1983/38] | Priority number, date | US19820357931 | 15.03.1982 Original published format: US 357931 | US19820364838 | 02.04.1982 Original published format: US 364838 | [1983/38] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0089221 | Date: | 21.09.1983 | Language: | EN | [1983/38] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 12.07.1983 | Classification | IPC: | H05K3/18, G03G13/00, C23C3/00, H01L21/308, H01L27/00 | [1983/38] | CPC: |
G03G15/1625 (EP);
G03G13/00 (EP);
G03G15/224 (EP);
G03G15/6585 (EP);
G03G15/6591 (EP);
G03G7/0093 (EP);
H05K3/182 (EP);
H05K2203/0517 (EP);
H05K3/102 (EP);
| Designated contracting states | DE, FR, GB, NL [1983/38] | Title | German: | Elektrographisches Verfahren zur Herstellung leitender Schaltungsmuster und auf diese Weise hergestellte Leiterplatten | [1983/38] | English: | Electrographic method of forming conductive circuit patterns and circuit boards formed thereby | [1983/38] | French: | Procédé électrographique pour la production des parcours conducteurs de circuits et panneaux de circuit produits de cette manière | [1983/38] | File destroyed: | 09.12.1992 | Examination procedure | 24.02.1984 | Examination requested [1984/18] | 01.10.1985 | Application deemed to be withdrawn, date of legal effect [1986/15] | 06.11.1985 | Despatch of communication that the application is deemed to be withdrawn, reason: renewal fee not paid in time [1986/15] | Fees paid | Penalty fee | Additional fee for renewal fee | 01.04.1985 | 03 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | DE1923028 [ ]; | US3779758 [ ]; | US4305975 [ ] |