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EP0130430
European procedure
Extract from the Register of European Patents
EP About this file: EP0130430
| EP0130430 - Method of generating circuit boards using electroeroded sheet layers and circuit boards so produced [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 30.01.1989 Database last updated on 28.09.2024 | Most recent event Tooltip | 30.01.1989 | No opposition filed within time limit | published on 22.03.1989 [1989/12] | Applicant(s) | For all designated states International Business Machines Corporation New Orchard Road Armonk, NY 10504 / US | [N/P] |
| Former [1985/02] | For all designated states International Business Machines Corporation Old Orchard Road Armonk, N.Y. 10504 / US | Inventor(s) | 01 /
Willie, Goff, Jr. 3908 Pebble Path Austin Texas 78737 / US | [1985/02] | Representative(s) | Arrabito, Michelangelo IBM ITALIA S.p.A. Direzione Brevetti MI-SEG-555 P.O. Box 137 I-20090 Segrate (Milano) / IT | [1985/02] | Application number, filing date | 84106836.4 | 15.06.1984 | [1985/02] | Priority number, date | US19830510540 | 05.07.1983 Original published format: US 510540 | [1985/02] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0130430 | Date: | 09.01.1985 | Language: | EN | [1985/02] | Type: | A3 Search report | No.: | EP0130430 | Date: | 30.04.1986 | Language: | EN | [1986/18] | Type: | B1 Patent specification | No.: | EP0130430 | Date: | 16.03.1988 | Language: | EN | [1988/11] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 13.03.1986 | Classification | IPC: | H05K3/46, H05K3/08 | [1985/02] | CPC: |
H05K3/08 (EP,US);
H05K3/368 (EP,US);
H05K1/09 (EP,US);
H05K2201/0323 (EP,US);
H05K2201/09609 (EP,US);
H05K2201/10378 (EP,US);
| Designated contracting states | DE, FR, GB [1985/02] | Title | German: | Verfahren zur Herstellung von Leiterplatten unter Verwendung von Lagen dünner Folien, die durch Elektroerosion behandelt wurden, und auf diese Weise hergestellte Leiterplatten | [1985/02] | English: | Method of generating circuit boards using electroeroded sheet layers and circuit boards so produced | [1985/02] | French: | Méthode pour fabriquer des plaquettes à circuit imprimé utilisant des couches à feuilles traitées par érosion électrique et des plaquettes à circuit imprimé fabriquées de cette façon | [1985/02] | File destroyed: | 15.01.2000 | Examination procedure | 23.11.1984 | Examination requested [1985/06] | 27.05.1987 | Despatch of communication of intention to grant (Approval: ) | 17.09.1987 | Communication of intention to grant the patent | 13.10.1987 | Fee for grant paid | 13.10.1987 | Fee for publishing/printing paid | Opposition(s) | 17.12.1988 | No opposition filed within time limit [1989/12] | Fees paid | Renewal fee | 24.06.1986 | Renewal fee patent year 03 | 23.06.1987 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP0074303 (ROUGE FRANCOIS); | [A]FR2333406 (SIEMENS AG [DE]) |