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EP0139165
European procedure
Extract from the Register of European Patents
EP About this file: EP0139165
| EP0139165 - Method of making a trench isolated integrated circuit device [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 16.05.1991 Database last updated on 15.06.2024 | Most recent event Tooltip | 16.05.1991 | No opposition filed within time limit | published on 03.07.1991 [1991/27] | Applicant(s) | For all designated states International Business Machines Corporation New Orchard Road Armonk, NY 10504 / US | [N/P] |
| Former [1985/18] | For all designated states International Business Machines Corporation Old Orchard Road Armonk, N.Y. 10504 / US | Inventor(s) | 01 /
Chesebro, Donald George 13 Cedar Ridge Drive Colchester, Vt. / US | 02 /
Soychak, Francis John 17 Colbert Street Essex Junction, Vt. / US | [1985/18] | Representative(s) | Gaugel, Heinz IBM Deutschland GmbH Schönaicher Strasse 220 D-7030 Böblingen / DE | [N/P] |
| Former [1989/39] | Gaugel, Heinz, Dipl.-Ing. IBM Deutschland GmbH Schönaicher Strasse 220 D-7030 Böblingen / DE | ||
| Former [1985/18] | Mönig, Anton, Dipl.-Ing. IBM Deutschland Informationssysteme GmbH, Patentwesen und Urheberrecht D-70548 Stuttgart / DE | Application number, filing date | 84110055.5 | 23.08.1984 | [1985/18] | Priority number, date | US19830539193 | 05.10.1983 Original published format: US 539193 | [1985/18] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0139165 | Date: | 02.05.1985 | Language: | EN | [1985/18] | Type: | A3 Search report | No.: | EP0139165 | Date: | 07.10.1987 | Language: | EN | [1987/41] | Type: | B1 Patent specification | No.: | EP0139165 | Date: | 11.07.1990 | Language: | EN | [1990/28] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 17.08.1987 | Classification | IPC: | H01L21/76, H01L21/31 | [1985/18] | CPC: |
H01L21/743 (EP,US);
H01L21/76232 (EP,US);
H01L29/7325 (EP,US)
| Designated contracting states | DE, FR, GB [1985/18] | Title | German: | Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit Isolierwannen | [1985/18] | English: | Method of making a trench isolated integrated circuit device | [1985/18] | French: | Procédé pour la fabrication d'un dispositif à circuit intégré comportant des rainures d'isolation | [1985/18] | Examination procedure | 23.11.1984 | Examination requested [1985/18] | 01.06.1989 | Despatch of a communication from the examining division (Time limit: M04) | 29.07.1989 | Reply to a communication from the examining division | 05.10.1989 | Despatch of communication of intention to grant (Approval: Yes) | 12.01.1990 | Communication of intention to grant the patent | 24.01.1990 | Fee for grant paid | 24.01.1990 | Fee for publishing/printing paid | Opposition(s) | 12.04.1991 | No opposition filed within time limit [1991/27] | Fees paid | Renewal fee | 19.08.1986 | Renewal fee patent year 03 | 21.08.1987 | Renewal fee patent year 04 | 23.08.1988 | Renewal fee patent year 05 | 21.08.1989 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]US4111724 (OGIUE KATUMI, et al); | [Y]FR2308204 (IBM [US]); | [A]GB2107926 (MONOLITHIC MEMORIES INC) | [Y] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 24, no. 7B, December 1981, pages 3861-3864, New York, US; C.G. JAMBOTKAR: "Method to fabricate very dense EPROM cell arrays" | [A] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 22, no. 3, August 1979, pages 1004-1007, New York, US; S.D. MALAVIYA et al.: "Bipolar process with self-aligned contacts and isolation" |