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EP0163132
European procedure
Extract from the Register of European Patents
EP About this file: EP0163132
| EP0163132 - A semiconductor memory device comprising a matrix of six-transistor memory cells with a pair of CMOS inverters [Right-click to bookmark this link] | |||
| Former [1985/49] | A semiconductor memory device comprised of sex-transistor memory cell with a pair of CMOS inverters | ||
| [1989/11] | Status | No opposition filed within time limit Status updated on 11.01.1990 Database last updated on 04.06.2024 | Most recent event Tooltip | 11.01.1990 | No opposition filed within time limit | published on 28.02.1990 [1990/09] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho, Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [1985/49] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP | Inventor(s) | 01 /
Masuoka, Fujio c/o Patent Division K.K. Toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | 02 /
Ochii, Kiyofumi c/o Patent Division K.K. Toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | [1989/11] |
| Former [1985/49] | 01 /
Masuoka, Fujio c/o Patent Division K.K. toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | ||
| 02 /
Ochii, Kiyofumi c/o Patent Division K.K. toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | Representative(s) | Lehn, Werner, et al Hoffmann Eitle, Patent- und Rechtsanwälte, Postfach 81 04 20 81904 München / DE | [N/P] |
| Former [1985/49] | Lehn, Werner, Dipl.-Ing., et al Hoffmann, Eitle & Partner, Patentanwälte, Postfach 81 04 20 D-81904 München / DE | Application number, filing date | 85105039.3 | 25.04.1985 | [1985/49] | Priority number, date | JP19840085617 | 27.04.1984 Original published format: JP 8561784 | JP19840085618 | 27.04.1984 Original published format: JP 8561884 | JP19840253026 | 30.11.1984 Original published format: JP 25302684 | JP19840253027 | 30.11.1984 Original published format: JP 25302784 | [1985/49] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0163132 | Date: | 04.12.1985 | Language: | EN | [1985/49] | Type: | B1 Patent specification | No.: | EP0163132 | Date: | 15.03.1989 | Language: | EN | [1989/11] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 04.09.1985 | Classification | IPC: | H01L27/10, H01L23/52, G11C11/40 | [1985/49] | CPC: |
H01L23/53271 (EP,US);
H01L29/94 (KR);
H10B10/12 (EP,US);
H01L2924/0002 (EP,US);
Y10S257/903 (EP,US)
| C-Set: |
H01L2924/0002, H01L2924/00 (EP,US)
| Designated contracting states | DE, FR, GB [1985/49] | Title | German: | Aus einer sechs-Transistor-Speicherzelle mit zwei CMOS-Invertern bestehende Halbleiter-Speichervorrichtung | [1985/49] | English: | A semiconductor memory device comprising a matrix of six-transistor memory cells with a pair of CMOS inverters | [1989/11] | French: | Dispositif de mémoire à semi-conducteur comprenant une cellule de mémoire à six transistors à deux inverseurs CMOS | [1985/49] |
| Former [1985/49] | A semiconductor memory device comprised of sex-transistor memory cell with a pair of CMOS inverters | Examination procedure | 25.04.1985 | Examination requested [1985/49] | 20.08.1987 | Despatch of a communication from the examining division (Time limit: M06) | 12.01.1988 | Reply to a communication from the examining division | 01.07.1988 | Despatch of communication of intention to grant (Approval: Yes) | 31.08.1988 | Communication of intention to grant the patent | 21.11.1988 | Fee for grant paid | 21.11.1988 | Fee for publishing/printing paid | Opposition(s) | 16.12.1989 | No opposition filed within time limit [1990/09] | Fees paid | Renewal fee | 15.04.1987 | Renewal fee patent year 03 | 15.04.1988 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]JP5661158 ; | [A]DE3002343 (NIPPON ELECTRIC CO); | [A]WO8102222 (MOSTEK CORP [US]); | [Y]EP0098737 (FUJITSU LTD [JP]) | [Y] - PATENT ABSTRACTS OF JAPAN, vol. 5, no. 125, 12th August 1981, page (E-69) (797); & JP-A-56-61158 (SUWA SEIKOSHA) 26-05-1981, & JP5661158 A 00000000 | [AD] - IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. SC-17, no. 5, October 1982, New York, USA; K. OCHII et al. "An Ultralow Power 8Kx8-Bit Full CMOS RAM with a Six-Transistor Cell", pages 798-803 |