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EP0170286
European procedure
Extract from the Register of European Patents
EP About this file: EP0170286
| EP0170286 - Semiconductor memory device [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 12.01.1991 Database last updated on 24.08.2024 | Most recent event Tooltip | 12.01.1991 | No opposition filed within time limit | published on 06.03.1991 [1991/10] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho, Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [1986/06] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP | Inventor(s) | 01 /
Sakurai, Takayasu c/o Patent Division Kabushiki Kaisha Toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | [1986/06] | Representative(s) | Lehn, Werner, et al Hoffmann Eitle, Patent- und Rechtsanwälte, Postfach 81 04 20 81904 München / DE | [N/P] |
| Former [1986/06] | Lehn, Werner, Dipl.-Ing., et al Hoffmann, Eitle & Partner, Patentanwälte, Postfach 81 04 20 D-81904 München / DE | Application number, filing date | 85109700.6 | 02.08.1985 | [1986/06] | Priority number, date | JP19840163510 | 03.08.1984 Original published format: JP 16351084 | [1986/06] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0170286 | Date: | 05.02.1986 | Language: | EN | [1986/06] | Type: | A3 Search report | No.: | EP0170286 | Date: | 07.10.1987 | Language: | EN | [1987/41] | Type: | B1 Patent specification | No.: | EP0170286 | Date: | 21.03.1990 | Language: | EN | [1990/12] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 17.08.1987 | Classification | IPC: | G11C8/00, G11C11/24, G11C11/40 | [1987/41] | CPC: |
G11C11/406 (EP,US);
H01L29/94 (KR)
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| Former IPC [1987/39] | G11C8/00, G11C11/24, G11C11/40 | ||
| Former IPC [1986/06] | G11C11/24 | Designated contracting states | DE, FR, GB [1986/06] | Title | German: | Halbleiterspeicheranordnung | [1986/06] | English: | Semiconductor memory device | [1986/06] | French: | Dispositif de mémoire semi-conductrice | [1986/06] | Examination procedure | 02.08.1985 | Examination requested [1986/06] | 01.03.1988 | Despatch of a communication from the examining division (Time limit: M06) | 09.09.1988 | Reply to a communication from the examining division | 12.10.1988 | Despatch of a communication from the examining division (Time limit: M04) | 15.02.1989 | Reply to a communication from the examining division | 05.07.1989 | Despatch of communication of intention to grant (Approval: Yes) | 20.09.1989 | Communication of intention to grant the patent | 20.12.1989 | Fee for grant paid | 20.12.1989 | Fee for publishing/printing paid | Opposition(s) | 22.12.1990 | No opposition filed within time limit [1991/10] | Fees paid | Renewal fee | 12.08.1987 | Renewal fee patent year 03 | 10.08.1988 | Renewal fee patent year 04 | 14.08.1989 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]JP53148348 ; | [Y]US4044339 (BERG ROBERT O); | [A]US4104719 (CHU WESLEY W, et al); | [A]DE2366265 (NIPPON ELECTRIC CO) | [Y] - PATENT ABSTRACTS OF JAPAN, vol. 3, no. 21 (E-92), 21st February 1979, page 35 E92; & JP-A-53 148 348 (TOKYO SHIBAURA DENKI K.K.) 23-12-1978, & JP53148348 A 00000000 | [A] - IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, San Francisco, 22nd-24th February 1984, vol. 27, Conf. 31, pages 214-215,340, IEEE, New York, US; M. ISOBE et al.: "A 46ns 256K CMOS RAM" | [A] - COMPUTER DESIGN, vol. 22, no. 3, March 1983, pages 111-122, Winchester, Massachusetts, US; J.J. FALLIN et al.: "The chip that refreshes itself" | [A] - ELECTRONIC ENGINEERING, vol. 53, no. 650, March 1981, page 27-30, London, GB; J. SCARISBRICK: "Large scale multi-port memories permit asynchronous operation" | Examination | US4330852 |