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EP0187260
European procedure
Extract from the Register of European Patents
EP About this file: EP0187260
| EP0187260 - Process for fabricating a semiconductor integrated circuit device having MISFETs [Right-click to bookmark this link] | |||
| Former [1986/29] | Semiconductor integrated-circuit device comprising a MISFET and process for producing the same | ||
| [1991/31] | Status | No opposition filed within time limit Status updated on 04.06.1992 Database last updated on 27.07.2024 | Most recent event Tooltip | 04.06.1992 | No opposition filed within time limit | published on 22.07.1992 [1992/30] | Applicant(s) | For all designated states Hitachi, Ltd. 6, Kanda Surugadai 4-chome Chiyoda-ku Tokyo / JP | [N/P] |
| Former [1986/29] | For all designated states HITACHI, LTD. 6, Kanda Surugadai 4-chome Chiyoda-ku, Tokyo 100 / JP | Inventor(s) | 01 /
Ikeda, Shuji 15-3, Midori-cho 5-chome Koganei-shi Tokyo / JP | 02 /
Koike, Atsuyoshi 21-11, Higashikoigakubo 2-chome Kokubunji-shi Tokyo / JP | 03 /
Meguro, Satoshi 2196-662, Hirai Hinode-machi Nishitama-gun Tokyo / JP | 04 /
Okuyama, Kousuke Hitachi Nishiki-sou 205 2-5, Nishiki-cho 6-chome Tachikawa-shi Tokyo / JP | [1986/29] | Representative(s) | Strehl Schübel-Hopf & Partner Maximilianstrasse 54 80538 München / DE | [N/P] |
| Former [1986/29] | Strehl Schübel-Hopf Groening & Partner Maximilianstrasse 54 D-80538 München / DE | Application number, filing date | 85115271.0 | 02.12.1985 | [1986/29] | Priority number, date | JP19840254010 | 03.12.1984 Original published format: JP 25401084 | [1986/29] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0187260 | Date: | 16.07.1986 | Language: | EN | [1986/29] | Type: | A3 Search report | No.: | EP0187260 | Date: | 07.01.1987 | Language: | EN | [1987/02] | Type: | B1 Patent specification | No.: | EP0187260 | Date: | 31.07.1991 | Language: | EN | [1991/31] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 18.11.1986 | Classification | IPC: | H01L21/82, H01L29/78, H01L27/08, H01L29/10, H01L29/08 | [1991/31] | CPC: |
H01L21/823807 (EP);
H01L29/76 (KR);
H01L27/088 (EP);
H01L27/0928 (EP);
H01L29/78 (EP);
H01L29/7838 (EP)
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| Former IPC [1986/29] | H01L29/78, H01L27/08, H01L29/10, H01L29/08, H01L21/82 | Designated contracting states | DE, FR, GB, IT [1986/29] | Title | German: | Verfahren zur Herstellung einer integrierten Halbleiterschaltungsanordnung, die MISFETs enthält | [1991/31] | English: | Process for fabricating a semiconductor integrated circuit device having MISFETs | [1991/31] | French: | Procédé pour fabriquer un dispositif à circuit intégré semi-conducteur comprenant des MISFETs | [1991/31] |
| Former [1986/29] | Integrierte Halbleiterschaltungsanordnung mit einem MISFET und Verfahren zu deren Herstellung | ||
| Former [1986/29] | Semiconductor integrated-circuit device comprising a MISFET and process for producing the same | ||
| Former [1986/29] | Dispositif à circuit intégré semi-conducteur comprenant un MISFET et procédé pour sa fabrication | Examination procedure | 30.06.1987 | Examination requested [1987/36] | 15.12.1989 | Despatch of a communication from the examining division (Time limit: M04) | 25.04.1990 | Reply to a communication from the examining division | 24.07.1990 | Despatch of communication of intention to grant (Approval: No) | 17.12.1990 | Despatch of communication of intention to grant (Approval: later approval) | 11.01.1991 | Communication of intention to grant the patent | 19.04.1991 | Fee for grant paid | 19.04.1991 | Fee for publishing/printing paid | Opposition(s) | 05.05.1992 | No opposition filed within time limit [1992/30] | Fees paid | Renewal fee | 29.12.1987 | Renewal fee patent year 03 | 23.12.1988 | Renewal fee patent year 04 | 28.12.1989 | Renewal fee patent year 05 | 27.12.1990 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]EP0113540 (WESTERN ELECTRIC CO [US]) | [X] - IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. ED-28, no. 7, July 1981, pages 888-890, IEEE, New York, US; K. YAMAGUCHI et al.: "Submicron gate MOSFET's with channel-doped separate gate structures (SG-MOSFET's)" | [X] - IEEE INTERNATIONAL ELECTRON DEVICES MEETING 1983, TECHNICAL DIGEST, Washington, D.C., US, 5th-7th December 1983, pages 340-343, IEEE, New York, US; R. MAUNTEL et al.: "A 1.5 micron HCMOS III technology for fast static RAMS" | [A] - IEEE TRANSACTION ON ELECTRON DEVICES, vol. ED-31, no. 2, February 1984, pages 205-214, IEEE, New York, US; T. YAMAGUCHI et al.: "Process and device performance of 1 mum-channel n-well CMOS technology" | [A] - IEEE INTERNATIONAL ELECTRON DEVICES MEETING 1978, TECHNICAL DIGEST, Washington, D.C., US, 4th-6th December 1978, pages 26-29; K. NISHIUCHI et al.: "A normally-off type buried channel MOSFET for VLSI circuits" |