Deutsch English Français

Contact

EP0184774

European procedure

Quick help

Maintenance news

Scheduled maintenance

Regular maintenance outages:
between 05.00 and 05.15 hrs CET (Monday to Sunday).

Other outages
Availability
Register Forum

2022.02.11

More...

News flashes

News flashes

New version of the European Patent Register - SPC information for Unitary Patents.

2024-03-06

More...

Extract from the Register of European Patents

EP About this file: EP0184774

EP0184774 - Memory arrangement and a switching stage comprising a memory arrangement for the establishment of dynamic connecting routes [Right-click to bookmark this link]
Status	The application is deemed to be withdrawn Status updated on 15.09.1989 Database last updated on 06.07.2024
Most recent event Tooltip	07.07.2007	Change - inventor	published on 08.08.2007 [2007/32]
Applicant(s)	For all designated states ALCATEL N.V. Strawinskylaan 537, (World Trade Center) NL-1077 XX Amsterdam / NL
	[1987/33]
Former [1986/25]	For all designated states International Standard Electric Corporation 320 Park Avenue New York New York 10022 / US
Inventor(s)	01 / Yudichak, Joseph Ronald 264 Opening Hill Road Madison, CT 06443 / US
	02 / Toegel, Herbert Joseph 77 Cross Road Middlebury, CT 06762 / US
	[1986/25]
Representative(s)	Villinger, Bernhard, et al Alcatel Intellectual Property Department, Stuttgart 70430 Stuttgart / DE
	[N/P]
Former [1986/25]	Villinger, Bernhard, Dipl.-Ing., et al Alcatel SEL AG Patent- und Lizenzwesen Postfach 30 09 29 D-70449 Stuttgart / DE
Application number, filing date	85115469.0	05.12.1985
	[1986/25]
Priority number, date	US19840682033	14.12.1984 Original published format: US 682033
	[1986/25]
Filing language	DE
Procedural language	DE
Publication	Type:	A2 Application without search report
	No.:	EP0184774
	Date:	18.06.1986
	Language:	DE
	[1986/25]
	Type:	A3 Search report
	No.:	EP0184774
	Date:	21.09.1988
	Language:	DE
	[1988/38]
Search report(s)	(Supplementary) European search report - dispatched on:	EP	04.08.1988
Classification	IPC:	H04Q11/04, G11C15/04, G11C8/00	[1988/35]
	CPC:	G11C15/04 (EP,US); H04Q11/06 (EP,US)
	Former IPC [1986/25]	H04Q11/04, G11C15/04
Designated contracting states	AT, DE, FR, GB, IT, NL, SE [1986/25]
Title	German:	Speicheranordnung und eine Speicheranordnung enthaltende Koppelstufe zum Herstellen von dynamisch zugeordneten Verbindungswegen	[1986/25]
	English:	Memory arrangement and a switching stage comprising a memory arrangement for the establishment of dynamic connecting routes	[1986/25]
	French:	Montage de mémoire et étage de commutation comprenant un montage de mémoire pour l'établissement de chemins de connexion dynamiques	[1986/25]
File destroyed:	12.05.1995
Examination procedure	22.03.1989	Application deemed to be withdrawn, date of legal effect [1989/44]
	09.06.1989	Despatch of communication that the application is deemed to be withdrawn, reason: examination fee not paid in time [1989/44]
Fees paid	Renewal fee
	23.12.1987	Renewal fee patent year 03
	Penalty fee
	Penalty fee Rule 85b EPC 1973
	14.04.1989	M01 Not yet paid
	Additional fee for renewal fee
	02.01.1989	04 M06 Not yet paid
Opt-out from the exclusive Tooltip competence of the Unified Patent Court	See the Register of the Unified Patent Court for opt-out data
	Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:	Search	[XP]JPS6033796 ;
		[X]CH517419 (IBM [US]);
		[A]FR2219597 (SIEMENS AG [DE]);
		[A]US3927396 (LE CAN CLAUDE JAN PRINCIPE FRE);
		[A]EP0010726 (CIT ALCATEL [FR]);
		[A]FR2454242 (SERVEL MICHEL);
		[A]US4244033 (HATTORI AKIRA);
		[A]FR2504760 (WESTERN ELECTRIC CO [US])
		[XP] - PATENT ABSTRACTS OF JAPAN, Band 9, Nr. 154, 28. Juni 1985Seite 1877 E 325; & JP-A-60 033 796 (NIPPON DENSHIN DENWA KOSHA) 21-02-1985
		[A] - IBM TECHNICAL DISCLOSURE BULLETIN, Band 26, Nr. 1, Juni 1983, Seiten 267-268, New YorkUS; M. DEMANGE: "Time-division switch cell using associative memories"
		[A] - INTERNATIONAL SWITCHING SYMPOSIUM, Paris, 7.-11. Mai 1979, Dokument 20B6, Seiten 267-274, ParisFR; K. MAWATARI et al.: "A distributed control digital data switching system"
		[A] - IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE, Band 25, Februar 1982, Seiten 206,207,323, New YorkUS; G. SURACE et al.: "A 256-Channel digital switch module IC"
		[A] - IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, Band 2, Boston, 19.-22. Juni 1983, Seiten 932-938IEEE; A.S. ACAMPORA et al.: "A centralized-bus architecture for local area networks"

The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.

Legal notice
Terms of use
24.1.24; 34p