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EP0180255
European procedure
Extract from the Register of European Patents
EP About this file: EP0180255
| EP0180255 - Semiconductor device comprising a bipolar transistor and an insulated-gate FET [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 20.12.1990 Database last updated on 14.09.2024 | Most recent event Tooltip | 20.12.1990 | No opposition filed within time limit | published on 06.02.1991 [1991/06] | Applicant(s) | For:GB
PHILIPS ELECTRONICS UK LIMITED 420-430 London Road Croydon CR9 3QR / GB | For:DE
FR
IT
NL
Koninklijke Philips Electronics N.V. Groenewoudseweg 1 5621 BA Eindhoven / NL | [N/P] |
| Former [1986/19] | For:GB
PHILIPS ELECTRONICS UK LIMITED 420-430 London Road Croydon CR9 3QR / GB | ||
| For:DE
FR
IT
NL
Philips Electronics N.V. Groenewoudseweg 1 NL-5621 BA Eindhoven / NL | Inventor(s) | 01 /
Coe, David James c/o Philips Research Laboratories Redhill Surrey RH1 5HA / GB | [1986/19] | Representative(s) | Stevens, Brian Thomas, et al Philips Electronics UK Limited Patents and Trade Marks Department Cross Oak Lane Redhill, Surrey RH1 5HA / GB | [1989/05] |
| Former [1988/10] | Stevens, Brian Thomas PHILIPS ELECTRONICS Patents and Trade Marks Department Centre Point New Oxford Street London WC1A 1QJ / GB | ||
| Former [1986/19] | Stevens, Brian Thomas Philips Electronics UK Limited Patents and Trade Marks Department Cross Oak Lane Redhill, Surrey RH1 5HA / GB | Application number, filing date | 85201381.2 | 03.09.1985 | [1986/19] | Priority number, date | GB19840023690 | 19.09.1984 Original published format: GB 8423690 | [1986/19] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0180255 | Date: | 07.05.1986 | Language: | EN | [1986/19] | Type: | A3 Search report | No.: | EP0180255 | Date: | 20.11.1986 | Language: | EN | [1986/47] | Type: | B1 Patent specification | No.: | EP0180255 | Date: | 28.02.1990 | Language: | EN | [1990/09] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 30.09.1986 | Classification | IPC: | H01L27/06 | [1986/19] | CPC: |
H01L27/0716 (EP,US);
H03K17/567 (EP,US)
| Designated contracting states | DE, FR, GB, IT, NL [1986/19] | Title | German: | Halbleiteranordnung mit einem Bipolar-Transistor und mit einem FET mit isolierendem Gate | [1986/19] | English: | Semiconductor device comprising a bipolar transistor and an insulated-gate FET | [1986/19] | French: | Dispositif semi-conducteur comprenant un transistor bipolaire et un FET à grille isolée | [1986/19] | Examination procedure | 09.04.1987 | Examination requested [1987/25] | 22.06.1989 | Despatch of communication of intention to grant (Approval: No) | 20.07.1989 | Despatch of communication of intention to grant (Approval: later approval) | 08.08.1989 | Communication of intention to grant the patent | 09.11.1989 | Fee for grant paid | 09.11.1989 | Fee for publishing/printing paid | Opposition(s) | 29.11.1990 | No opposition filed within time limit [1991/06] | Fees paid | Renewal fee | 21.09.1987 | Renewal fee patent year 03 | 22.08.1988 | Renewal fee patent year 04 | 27.09.1989 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]JP5773964 ; | [A]EP0118336 (FAIRCHILD CAMERA INSTR CO [US]); | [A]FR2524711 (GEN ELECTRIC [US]) | [A] - IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, Washington, DC, US, 5th-7th December 1983, pages 59-62, IEEE, New York, US; F. WALCZYK et al.: "A merged CMOS/bipolar VLSI process" | [A] - PATENTS ABSTRACTS OF JAPAN, vol. 6, no. 151 (E-124)[1029], 11th August 1982; & JP - A - 57 73 964 (OKI DENKI KOGYO K.K.) 08-05-1982, & JP5773964 A 00000000 | [A] - ELEKTRONIK, vol. 31, no. 10, 8th October 1982, pages 71-75, Munich, DE; B.R. PELLY: "Leistungshalbleiter - ein Überblick" |