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EP0186411
European procedure
Extract from the Register of European Patents
EP About this file: EP0186411
| EP0186411 - Semiconductor device in which a semiconductor chip is fixed to a base [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 28.12.1991 Database last updated on 19.10.2024 | Most recent event Tooltip | 28.12.1991 | No opposition filed within time limit | published on 19.02.1992 [1992/08] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho, Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [1986/27] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP | Inventor(s) | 01 /
Takemura, Momoko c/o Patent Division Kabushiki Kaisha Toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | 02 /
Inaba, Michihiko c/o Patent Division Kabushiki Kaisha Toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | 03 /
Tetsuya, Toshio c/o Patent Division Kabushiki Kaisha Toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | 04 /
Kobayashi, Mitsuo c/o Patent Division Kabushiki Kaisha Toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | [1986/27] | Representative(s) | Freed, Arthur Woolf, et al Marks & Clerk Incorporating Edward Evans Barker 90 Long Acre London WC2E 9RA / GB | [N/P] |
| Former [1986/27] | Freed, Arthur Woolf, et al MARKS & CLERK, 57-60 Lincoln's Inn Fields London WC2A 3LS / GB | Application number, filing date | 85309170.0 | 16.12.1985 | [1986/27] | Priority number, date | JP19840276075 | 28.12.1984 Original published format: JP 27607584 | JP19840276077 | 28.12.1984 Original published format: JP 27607784 | JP19840276104 | 28.12.1984 Original published format: JP 27610484 | [1986/27] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0186411 | Date: | 02.07.1986 | Language: | EN | [1986/27] | Type: | A3 Search report | No.: | EP0186411 | Date: | 01.04.1987 | Language: | EN | [1987/14] | Type: | B1 Patent specification | No.: | EP0186411 | Date: | 27.02.1991 | Language: | EN | [1991/09] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 10.02.1987 | Classification | IPC: | H01L23/48 | [1986/27] | CPC: |
H01L24/27 (EP,US);
B23K35/001 (EP,US);
B23K35/302 (EP,US);
H01L21/50 (KR);
H01L21/60 (KR);
H01L23/4924 (EP,US);
H01L24/29 (EP,US);
H01L24/32 (EP,US);
H01L24/83 (EP,US);
B23K2035/008 (EP,US);
H01L2224/274 (EP,US);
H01L2224/29101 (EP,US);
H01L2224/29111 (EP,US);
H01L2224/32245 (EP,US);
H01L2224/48091 (EP,US);
H01L2224/48247 (EP,US);
H01L2224/49171 (EP,US);
H01L2224/73265 (EP,US);
H01L2224/8319 (EP,US);
H01L2224/83801 (EP,US);
H01L24/48 (EP,US);
H01L24/49 (EP,US);
H01L2924/00014 (EP,US);
H01L2924/01005 (EP,US);
H01L2924/01006 (EP,US);
H01L2924/01013 (EP,US);
H01L2924/01015 (EP,US);
H01L2924/01019 (EP,US);
H01L2924/01023 (EP,US);
H01L2924/01024 (EP,US);
H01L2924/01027 (EP,US);
H01L2924/01029 (EP,US);
H01L2924/0103 (EP,US);
H01L2924/01032 (EP,US);
H01L2924/01033 (EP,US);
H01L2924/0104 (EP,US);
H01L2924/01041 (EP,US);
H01L2924/0105 (EP,US);
H01L2924/01058 (EP,US);
H01L2924/01061 (EP,US);
H01L2924/01079 (EP,US);
H01L2924/01082 (EP,US);
H01L2924/0132 (EP,US);
H01L2924/01322 (EP,US);
H01L2924/014 (EP,US);
| C-Set: |
H01L2224/29101, H01L2924/014, H01L2924/00 (US,EP);
H01L2224/29111, H01L2924/01029, H01L2924/00014 (EP,US);
H01L2224/29111, H01L2924/01082, H01L2924/00014 (EP,US);
H01L2224/48091, H01L2924/00014 (US,EP);
H01L2224/73265, H01L2224/32245, H01L2224/48247 (US,EP);
H01L2924/00014, H01L2224/45099 (US,EP);
H01L2924/0132, H01L2924/01029, H01L2924/0105 (EP,US);
H01L2924/0132, H01L2924/01032, H01L2924/01079 (US,EP); | Designated contracting states | DE, FR, GB [1986/27] | Title | German: | Halbleiteranordnung worin ein Halbleiterchip auf einer Basis befestigt ist | [1986/27] | English: | Semiconductor device in which a semiconductor chip is fixed to a base | [1986/27] | French: | Dispositif semi-conducteur dans lequel une puce semi-conductrice est fixée sur une embase | [1986/27] | Examination procedure | 02.10.1986 | Examination requested [1986/49] | 08.09.1989 | Despatch of a communication from the examining division (Time limit: M06) | 09.01.1990 | Reply to a communication from the examining division | 26.02.1990 | Despatch of communication of intention to grant (Approval: Yes) | 30.05.1990 | Communication of intention to grant the patent | 29.08.1990 | Fee for grant paid | 29.08.1990 | Fee for publishing/printing paid | Opposition(s) | 28.11.1991 | No opposition filed within time limit [1992/08] | Fees paid | Renewal fee | 09.12.1987 | Renewal fee patent year 03 | 16.12.1988 | Renewal fee patent year 04 | 18.12.1989 | Renewal fee patent year 05 | 11.12.1990 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XD]GB2138633 (TOSHIBA KK); | [Y]WO8202457 (MOSTEK CORP [US], et al); | [A]EP0070435 (MATSUSHITA ELECTRONICS CORP [JP]); | [A]DE3312713 (FURUKAWA ELECTRIC CO LTD [JP]) |