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EP0198468
European procedure
Extract from the Register of European Patents
EP About this file: EP0198468
| EP0198468 - Protective device for integrated circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 27.08.1992 Database last updated on 11.04.2026 | Most recent event Tooltip | 27.08.1992 | No opposition filed within time limit | published on 14.10.1992 [1992/42] | Applicant(s) | For all designated states NEC Corporation 7-1, Shiba 5-chome Minato-ku Tokyo 108-8001 / JP | [N/P] |
| Former [1986/43] | For all designated states NEC CORPORATION 7-1, Shiba 5-chome Minato-ku Tokyo / JP | Inventor(s) | 01 /
Fujii, Takeo c/o NEC Corporation 33-1, Shiba 5-chome Minato-ku Tokyo / JP | [1986/43] | Representative(s) | Glawe, Delfs, Moll Partnerschaft mbB von Patent- und Rechtsanwälten Postfach 26 01 62 80058 München / DE | [N/P] |
| Former [1986/43] | Glawe, Delfs, Moll & Partner Patentanwälte Postfach 26 01 62 D-80058 München / DE | Application number, filing date | 86105169.6 | 15.04.1986 | [1986/43] | Priority number, date | JP19850079645 | 15.04.1985 Original published format: JP 7964585 | [1986/43] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0198468 | Date: | 22.10.1986 | Language: | EN | [1986/43] | Type: | A3 Search report | No.: | EP0198468 | Date: | 22.04.1987 | Language: | EN | [1987/17] | Type: | B1 Patent specification | No.: | EP0198468 | Date: | 23.10.1991 | Language: | EN | [1991/43] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 05.03.1987 | Classification | IPC: | H01L27/02, H01L29/06 | [1986/43] | CPC: |
H10D89/811 (EP)
| Designated contracting states | DE, FR, GB [1986/43] | Title | German: | Schutzanordnung für eine integrierte Schaltung | [1986/43] | English: | Protective device for integrated circuit | [1986/43] | French: | Dispositif de protection pour circuit intégré | [1986/43] | Examination procedure | 15.04.1986 | Examination requested [1986/43] | 05.12.1989 | Despatch of a communication from the examining division (Time limit: M06) | 15.05.1990 | Reply to a communication from the examining division | 12.07.1990 | Despatch of a communication from the examining division (Time limit: M04) | 15.11.1990 | Reply to a communication from the examining division | 17.12.1990 | Despatch of communication of intention to grant (Approval: Yes) | 26.04.1991 | Communication of intention to grant the patent | 30.07.1991 | Fee for grant paid | 30.07.1991 | Fee for publishing/printing paid | Opposition(s) | 24.07.1992 | No opposition filed within time limit [1992/42] | Fees paid | Renewal fee | 20.04.1988 | Renewal fee patent year 03 | 20.04.1989 | Renewal fee patent year 04 | 20.04.1990 | Renewal fee patent year 05 | 22.04.1991 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A] JP5851555 | [X] MICROELECTRONICS AND RELIABILITY, vol. 22, no. 2, 1982,pages 187-193, Pergamon Press LTD, Oxford, GB; C.A.MILLER et al.: "Punch-through gate protection of M.O.S. devices" [X] | [A] PATENTS ABSTRACTS OF JAPAN, vol. 7, no. 136 (E-181)[1281], 14th June 1983; & JP-A-58 51 555 (NIPPON DENSO K.K.) 26-03-1983 [A] | [A] IEEE-11th ANNUAL PROCEEDINGS RELIABILITY PHYSICS, Las Vegas, 3th-5th April 1973, pages 198-202, IEEE, New York, US; L.W.LINHOLM et al.: "Electrostatic gate protection using an arc gap device" [A] | [A] IEEE Transactions on electron devices, vol. ED-25, no. 8, August 1978, pages 926-932, IEEE, New York, US; S.H.COHEN et al.: "An improved input protection circuit for C-Mos/SOS arrays" [A] |