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EP0252999
European procedure
Extract from the Register of European Patents
EP About this file: EP0252999
| EP0252999 - Clocked CMOS circuit with at least one CMOS switch [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 25.02.1993 Database last updated on 05.10.2024 | Most recent event Tooltip | 25.02.1993 | No opposition filed within time limit | published on 14.04.1993 [1993/15] | Applicant(s) | For all designated states Deutsche ITT Industries GmbH Hans-Bunte-Strasse 19 79108 Freiburg / DE | [N/P] |
| Former [1988/03] | For all designated states Deutsche ITT Industries GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg / DE | Inventor(s) | 01 /
Theus, Ulrich, Dr. Ing. Schönbergstrasse 5b D-7803 Gundelfingen / DE | 02 /
Orben, Hans-Josef, Dipl.-Ing. (FH) Bergstrasse 7 D-7803 Heuweiler / DE | [1988/03] | Representative(s) | (deleted) | [1989/10] |
| Former [1988/03] | Morstadt, Volker, Dipl.-Ing. Deutsche ITT Industries GmbH, Patentabteilung, Hans-Bunte-Strasse 19 D-79108 Freiburg / DE | Application number, filing date | 86109362.3 | 09.07.1986 | [1988/03] | Filing language | DE | Procedural language | DE | Publication | Type: | A1 Application with search report | No.: | EP0252999 | Date: | 20.01.1988 | Language: | DE | [1988/03] | Type: | B1 Patent specification | No.: | EP0252999 | Date: | 22.04.1992 | Language: | DE | [1992/17] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 26.03.1987 | Classification | IPC: | H03K17/693, H03K17/687 | [1988/03] | CPC: |
H03K3/356121 (EP,US);
H03K17/6872 (EP,US);
H03K17/693 (EP,US);
H03K3/0375 (EP,US)
| Designated contracting states | DE, FR, NL [1988/26] |
| Former [1988/03] | DE, FR, GB, IT, NL | Title | German: | Getaktete CMOS-Schaltung mit mindestens einem CMOS-Schalter | [1988/03] | English: | Clocked CMOS circuit with at least one CMOS switch | [1988/03] | French: | Circuit CMOS à commande d'horloge comportant au moins un interrupteur CMOS | [1988/03] | Examination procedure | 10.07.1987 | Loss of particular rights, legal effect: designated state(s) | 02.10.1987 | Despatch of communication of loss of particular rights: designated state(s) GB, IT | 11.04.1988 | Examination requested [1988/23] | 22.05.1990 | Despatch of a communication from the examining division (Time limit: M06) | 11.10.1990 | Reply to a communication from the examining division | 26.07.1991 | Despatch of communication of intention to grant (Approval: Yes) | 24.10.1991 | Communication of intention to grant the patent | 18.01.1992 | Fee for grant paid | 18.01.1992 | Fee for publishing/printing paid | Opposition(s) | 23.01.1993 | No opposition filed within time limit [1993/15] | Fees paid | Renewal fee | 25.07.1988 | Renewal fee patent year 03 | 10.07.1989 | Renewal fee patent year 04 | 17.07.1990 | Renewal fee patent year 05 | 20.12.1990 | Renewal fee patent year 06 | Penalty fee | Penalty fee Rule 85a EPC 1973 | 09.07.1987 | GB M02 Not yet paid | 09.07.1987 | IT M02 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]JP5871717 ; | [Y]JP5830231 ; | [A]JP53101260 ; | [A]US3986046 (WUNNER JOHN J); | [Y]US4001606 (DINGWALL ANDREW GORDON FRANCIS); | [AD]EP0115834 (TOKYO SHIBAURA ELECTRIC CO [JP]); | [A]US4508983 (ALLGOOD ROBERT N [US], et al) | [Y] - PATENTS ABSTRACTS OF JAPAN, Band 7, Nr. 166 (E-188)[1311], 21. Juli 1983; & JP-A-58 71 717 (HITACHI SEISAKUSHO K.K.) 28-04-1983, & JP5871717 A 00000000 | [Y] - PATENTS ABSTRACTS OF JAPAN, Band 7, Nr. 111 (E-175)[1256], 14. Mai 1983; & JP-A-58 30 231 (EPUSON K.K.) 22-02-1983, & JP5830231 A 00000000 | [A] - PATENTS ABSTRACTS OF JAPAN, Band 7, Nr. 133 (E-78)[8221], 8. November 1978; & JP-A-53 101 260 (MITSUBISHI DENKI K.K.) 09-04-1978, & JP53101260 A 00000000 | [A] - IEEE JOURNAL OF SOLID-STATE CIRCUITS, Band SC-18, Nr. 3, Juni 1983, Seiten 369-376, IEEE, New York, US; M. ROCCHI et al.: "GaAs digital dynamic IC's for applications up to 10 GHz" | [A] - IEEE JOURNAL OF SOLID-STATE CIRCUITS, Band SC-18, Nr. 3, Juni 1983, Seiten 261-266, IEEE, New York, US; N.F. GONCALVES: "NORA: A racefree dynamic CMOS technique for pipelined logic structures" | [A] - IEEE TRANSACTIONS ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING, Band 32, Nr. 1, Februar 1984, Seiten 28-33, IEEE, New York, US; P.R. CAPPELLO et al.: "Optimal choice of intermediate latching to maximize throughput in VSLI circuits" |