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EP0211353
European procedure
Extract from the Register of European Patents
EP About this file: EP0211353
| EP0211353 - Method for the manufacture of a field effect transistor [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 23.04.1992 Database last updated on 09.04.2026 | Most recent event Tooltip | 23.04.1992 | No opposition filed within time limit | published on 10.06.1992 [1992/24] | Applicant(s) | For all designated states NIPPON TELEGRAPH AND TELEPHONE CORPORATION 1-6 Uchisaiwai-cho 1-chome Chiyoda-ku Tokyo 100 / JP | [N/P] |
| Former [1987/09] | For all designated states Nippon Telegraph and Telephone Corporation 1-6 Uchisaiwai-cho 1-chome Chiyoda-ku Tokyo 100 / JP | Inventor(s) | 01 /
Enoki, Takamoto Soubudai-Ryo 2-183, Soubudai Zama-shi Kanagawa 228 / JP | 02 /
Yamasaki, Kimiyoshi Denden 5-101, 861-1 Ishida Isehara-shi Kanagawa 259-11 / JP | 03 /
Ohwada, Kuniki 1074-47, Katakura-cho Hachioji-shi Tokyo 192 / JP | [1987/09] | Representative(s) | Sunderland, James Harry, et al Haseltine Lake LLP Lincoln House 300 High Holborn London WC1V 7JH / GB | [N/P] |
| Former [1987/09] | Sunderland, James Harry, et al HASELTINE LAKE & CO Hazlitt House 28 Southampton Buildings Chancery Lane London WC2A 1AT / GB | Application number, filing date | 86110293.7 | 25.07.1986 | [1987/09] | Priority number, date | JP19850167304 | 29.07.1985 Original published format: JP 16730485 | [1987/09] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0211353 | Date: | 25.02.1987 | Language: | EN | [1987/09] | Type: | A3 Search report | No.: | EP0211353 | Date: | 19.11.1987 | Language: | EN | [1987/47] | Type: | B1 Patent specification | No.: | EP0211353 | Date: | 19.06.1991 | Language: | EN | [1991/25] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 28.09.1987 | Classification | IPC: | H01L21/28 | [1987/09] | CPC: |
H10D30/0614 (EP,US);
H10D64/0125 (EP,US);
Y10S148/139 (EP,US)
| Designated contracting states | DE, FR, GB [1987/09] | Title | German: | Verfahren zur Herstellung eines Feldeffekttransistors | [1987/09] | English: | Method for the manufacture of a field effect transistor | [1987/09] | French: | Méthode de fabrication d'un transistor à effet de champ | [1987/09] | Examination procedure | 29.01.1988 | Examination requested [1988/13] | 09.10.1989 | Despatch of a communication from the examining division (Time limit: M06) | 18.04.1990 | Reply to a communication from the examining division | 05.07.1990 | Despatch of communication of intention to grant (Approval: No) | 07.12.1990 | Despatch of communication of intention to grant (Approval: later approval) | 14.12.1990 | Communication of intention to grant the patent | 07.03.1991 | Fee for grant paid | 07.03.1991 | Fee for publishing/printing paid | Opposition(s) | 20.03.1992 | No opposition filed within time limit [1992/24] | Fees paid | Renewal fee | 13.07.1988 | Renewal fee patent year 03 | 18.07.1989 | Renewal fee patent year 04 | 17.07.1990 | Renewal fee patent year 05 | 28.12.1990 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y] JP57103364 | [Y] PATENT ABSTRACTS OF JAPAN, vol. 6, no. 189 (E-133)[1067], 28th September 1982; & JP-A-57 103 364 (NIPPON DENSHIN DENWA KOSHA) 26-06-1982 [Y] | [Y] IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. ED-29, no. 11, November 1982, pages 1772-1777, IEEE, New York, US; KIMIYOSHI YAMASAKI et al.: "GaAs LSI-directed MESFET's with a self-aligned implantation for n+-layer technology (SAINT)" [Y] | [A] IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. ED-25, no. 10, October 1978, pages 1213-1218, IEEE, New York, US; SUSUMU TAKAHASHI et al.: "Submicrometer gate fabrication of GaAs MESFET by plasma etching" [A] | [XP] JAPANESE JOURNAL OF APPLIED PHYSICS, supplements 17th Conference on Solid State Devices and Materials, 25th-27th August 1985, pages 413-416, Tokyo, JP; T. ENOKI et al.: "Advanced GaAs SAINT FET fabrication technology and its application to above 9 GHz frequency divider" [XP] |