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EP0217091
European procedure
Extract from the Register of European Patents
EP About this file: EP0217091
| EP0217091 - Velocity error correcting circuit for time base error corrector [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 22.10.1992 Database last updated on 11.09.2024 | Most recent event Tooltip | 22.10.1992 | No opposition filed within time limit | published on 09.12.1992 [1992/50] | Applicant(s) | For all designated states Sony Corporation 7-35 Kitashinagawa 6-chome Shinagawa-ku Tokyo 141 / JP | [N/P] |
| Former [1987/15] | For all designated states SONY CORPORATION 7-35 Kitashinagawa 6-chome Shinagawa-ku Tokyo 141 / JP | Inventor(s) | 01 /
Kaneko, Shinji c/o Sony Corporation 6-7-35 Kitashinagawa Shinagawa-ku Tokyo / JP | 02 /
Takanashi, Kenji c/o Sony Corporation 6-7-35 Kitashinagawa Shinagawa-ku Tokyo / JP | 03 /
Wakisaka, Yoshiaki c/o Sony Corporation 6-7-35 Kitashinagawa Shinagawa-ku Tokyo / JP | [1987/15] | Representative(s) | Ter Meer Steinmeister & Partner Patentanwälte mbB Nymphenburger Strasse 4 80335 München / DE | [N/P] |
| Former [1987/15] | TER MEER - MÜLLER - STEINMEISTER & PARTNER Mauerkircherstrasse 45 D-81679 München / DE | Application number, filing date | 86111373.6 | 18.08.1986 | [1987/15] | Priority number, date | JP19850181452 | 19.08.1985 Original published format: JP 18145285 | JP19850270530 | 30.11.1985 Original published format: JP 27053085 | [1987/15] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0217091 | Date: | 08.04.1987 | Language: | EN | [1987/15] | Type: | B1 Patent specification | No.: | EP0217091 | Date: | 18.12.1991 | Language: | EN | [1991/51] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 03.02.1987 | Classification | IPC: | H04N5/95 | [1987/15] | CPC: |
H04N9/896 (EP,US);
H04N5/95 (KR)
| Designated contracting states | AT, DE, FR, GB, NL [1987/15] | Title | German: | Korrekturkreis für Geschwindigkeitsfehler in einem Zeitbasiskorrektor | [1987/15] | English: | Velocity error correcting circuit for time base error corrector | [1987/15] | French: | Circuit de correction d'erreurs de vitesse dans un correcteur de base de temps | [1987/15] | Examination procedure | 07.10.1987 | Examination requested [1987/49] | 13.07.1990 | Despatch of a communication from the examining division (Time limit: M04) | 13.11.1990 | Reply to a communication from the examining division | 18.02.1991 | Despatch of communication of intention to grant (Approval: Yes) | 24.06.1991 | Communication of intention to grant the patent | 25.09.1991 | Fee for grant paid | 25.09.1991 | Fee for publishing/printing paid | Opposition(s) | 19.09.1992 | No opposition filed within time limit [1992/50] | Fees paid | Renewal fee | 16.08.1988 | Renewal fee patent year 03 | 16.08.1989 | Renewal fee patent year 04 | 14.08.1990 | Renewal fee patent year 05 | 31.12.1990 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | US4165524 [ ] (NINOMIYA TAKESHI); | DE3109280 [ ] (SONY CORP [JP]); | DE3200291 [ ] (SONY CORP [JP]) |