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EP0217348
European procedure
Extract from the Register of European Patents
EP About this file: EP0217348
| EP0217348 - Memory connected state detecting circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 09.09.1995 Database last updated on 24.08.2024 | Most recent event Tooltip | 09.09.1995 | No opposition filed within time limit | published on 02.11.1995 [1995/44] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho, Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [1987/15] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP | Inventor(s) | 01 /
Todaka, Seiji 1-16 Furuichiba Saiwai-ku Kawasaki-shi Kanagawa-ken / JP | [1987/15] | Representative(s) | Eitle, Werner, et al Hoffmann Eitle, Patent- und Rechtsanwälte, Postfach 81 04 20 81904 München / DE | [N/P] |
| Former [1987/15] | Eitle, Werner, Dipl.-Ing., et al Hoffmann, Eitle & Partner, Patent- und Rechtsanwälte, Postfach 81 04 20 D-81904 München / DE | Application number, filing date | 86113400.5 | 30.09.1986 | [1987/15] | Priority number, date | JP19850217131 | 30.09.1985 Original published format: JP 21713185 | [1987/15] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0217348 | Date: | 08.04.1987 | Language: | EN | [1987/15] | Type: | A3 Search report | No.: | EP0217348 | Date: | 08.11.1989 | Language: | EN | [1989/45] | Type: | B1 Patent specification | No.: | EP0217348 | Date: | 09.11.1994 | Language: | EN | [1994/45] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 19.09.1989 | Classification | IPC: | G06F12/00 | [1987/15] | CPC: |
G06F12/0684 (EP,US);
G11C29/00 (KR);
G06F12/00 (KR);
G06F12/16 (KR)
| Designated contracting states | DE, FR, GB [1987/15] | Title | German: | Schaltung zur Speicherschaltzustanderkennung | [1987/15] | English: | Memory connected state detecting circuit | [1987/15] | French: | Circuit de détection de l'état connecté d'une mémoire | [1987/15] | Examination procedure | 30.09.1986 | Examination requested [1987/15] | 27.07.1992 | Despatch of a communication from the examining division (Time limit: M04) | 27.11.1992 | Reply to a communication from the examining division | 13.09.1993 | Despatch of a communication from the examining division (Time limit: M02) | 23.11.1993 | Reply to a communication from the examining division | 07.01.1994 | Despatch of communication of intention to grant (Approval: Yes) | 11.04.1994 | Communication of intention to grant the patent | 22.06.1994 | Fee for grant paid | 22.06.1994 | Fee for publishing/printing paid | Opposition(s) | 10.08.1995 | No opposition filed within time limit [1995/44] | Fees paid | Renewal fee | 14.09.1988 | Renewal fee patent year 03 | 11.09.1989 | Renewal fee patent year 04 | 21.09.1990 | Renewal fee patent year 05 | 09.09.1991 | Renewal fee patent year 06 | 15.09.1992 | Renewal fee patent year 07 | 16.09.1993 | Renewal fee patent year 08 | 08.09.1994 | Renewal fee patent year 09 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]US3815103 (HOLTEY T, et al); | [Y]US4486855 (DUKE JACK R [US]); | [A]EP0051905 (BRITISH GAS CORP [GB]) | [A] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 22, no. 10, March 1980, pages 4366-4368, New York, US; L.C. EGGEBRECHT et al.: "Parity check circuit for detecting missing feature cards" |