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EP0228206

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Extract from the Register of European Patents

EP About this file: EP0228206

EP0228206 - Method of making an integrated circuit structure having gate electrode and underlying oxide [Right-click to bookmark this link]
Former [1987/28]	Improvements in integrated circuit structure having gate electrode and underlying oxide and method of making same
	[1994/07]
Status	No opposition filed within time limit Status updated on 22.12.1994 Database last updated on 24.04.2024
Most recent event Tooltip	28.11.2003	Lapse of the patent in a contracting state New state(s): ES	published on 14.01.2004 [2004/03]
Applicant(s)	For all designated states ADVANCED MICRO DEVICES, INC. 901 Thompson Place P.O. Box 3453 Sunnyvale CA 94088-3453 / US
	[N/P]
Former [1987/28]	For all designated states ADVANCED MICRO DEVICES, INC. 901 Thompson Place P.O. Box 3453 Sunnyvale, CA 94088 / US
Inventor(s)	01 / Cox, William P. 570 Meadow Avenue Santa Clara California 95051 / US
	02 / Liang, Mong-Song 792 Los Positos Dr. Milpitas California 95035 / US
	[1987/28]
Representative(s)	Wright, Hugh Ronald, et al Brookes Batchellor LLP 1 Boyne Park Tunbridge Wells Kent TN4 8EL / GB
	[N/P]
Former [1987/28]	Wright, Hugh Ronald, et al Brookes & Martin 52/54 High Holborn London WC1V 6SE / GB
Application number, filing date	86309559.2	09.12.1986
	[1987/28]
Priority number, date	US19850811057	17.12.1985 Original published format: US 811057
	[1987/28]
Filing language	EN
Procedural language	EN
Publication	Type:	A2 Application without search report
	No.:	EP0228206
	Date:	08.07.1987
	Language:	EN
	[1987/28]
	Type:	A3 Search report
	No.:	EP0228206
	Date:	27.04.1988
	Language:	EN
	[1988/17]
	Type:	B1 Patent specification
	No.:	EP0228206
	Date:	16.02.1994
	Language:	EN
	[1994/07]
Search report(s)	(Supplementary) European search report - dispatched on:	EP	07.03.1988
Classification	IPC:	H01L21/28, H01L29/784, G11C17/00	[1994/07]
	CPC:	H01L29/7883 (EP,US); H01L29/40114 (EP,US); H01L29/4916 (EP,US)
	Former IPC [1987/28]	H01L29/60, H01L29/78, H01L21/28, // G11C17/00
Designated contracting states	AT, BE, CH, DE, ES, FR, GB, GR, IT, LI, LU, NL, SE [1987/28]
Title	German:	Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit Gate-Elektrode und unterliegendem Oxid	[1994/07]
	English:	Method of making an integrated circuit structure having gate electrode and underlying oxide	[1994/07]
	French:	Méthode de fabrication d'une structure de circuit intégré ayant une électrode de grille et une sous-couche d'oxyde	[1994/07]
	Former [1987/28]	Integrierte Schaltungsanordnung mit Gate-Elektrode und unterliegendem Oxid und Verfahren zu ihrer Herstellung
	Former [1987/28]	Improvements in integrated circuit structure having gate electrode and underlying oxide and method of making same
	Former [1987/28]	Structure de circuit intégré ayant une électrode de grille et une sous-couche d'oxyde et sa méthode de fabrication
Examination procedure	18.04.1988	Examination requested [1988/24]
	07.07.1992	Despatch of a communication from the examining division (Time limit: M04)
	01.10.1992	Reply to a communication from the examining division
	14.01.1993	Despatch of a communication from the examining division (Time limit: M02)
	11.03.1993	Reply to a communication from the examining division
	01.07.1993	Despatch of communication of intention to grant (Approval: Yes)
	13.08.1993	Communication of intention to grant the patent
	27.10.1993	Fee for grant paid
	27.10.1993	Fee for publishing/printing paid
Opposition(s)	18.11.1994	No opposition filed within time limit [1995/07]
Fees paid	Renewal fee
	22.12.1988	Renewal fee patent year 03
	20.12.1989	Renewal fee patent year 04
	18.12.1990	Renewal fee patent year 05
	20.12.1991	Renewal fee patent year 06
	30.10.1992	Renewal fee patent year 07
	24.11.1993	Renewal fee patent year 08
Opt-out from the exclusive Tooltip competence of the Unified Patent Court	See the Register of the Unified Patent Court for opt-out data
	Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition Tooltip	AT	16.02.1994
	BE	16.02.1994
	CH	16.02.1994
	GR	16.02.1994
	LI	16.02.1994
	NL	16.02.1994
	SE	16.02.1994
	ES	27.05.1994
	[2004/03]
Former [2000/04]	AT	16.02.1994
	BE	16.02.1994
	CH	16.02.1994
	GR	16.02.1994
	LI	16.02.1994
	NL	16.02.1994
	SE	16.02.1994
Former [1995/10]	AT	16.02.1994
	BE	16.02.1994
	CH	16.02.1994
	LI	16.02.1994
	NL	16.02.1994
	SE	16.02.1994
Former [1994/49]	AT	16.02.1994
	BE	16.02.1994
	CH	16.02.1994
	LI	16.02.1994
	SE	16.02.1994
Former [1994/47]	AT	16.02.1994
	CH	16.02.1994
	LI	16.02.1994
	SE	16.02.1994
Former [1994/46]	AT	16.02.1994
	SE	16.02.1994
Former [1994/45]	SE	16.02.1994
Documents cited:	Search	[X]JP56026469 ;
		[X]JP58212178 ;
		[X]US4288256 (NING TAK H, et al);
		[X]EP0053013 (FUJITSU LTD [JP]);
		[X]WO8302197 (NCR CO [US]);
		[A]GB2130009 (RCA CORP);
		[X]EP0160965 (TOSHIBA KK [JP])
		[X] - PATENT ABSTRACT OF JAPAN, vol. 5, no. 78 (E-58)[750], 22nd May 1981; & JP-A-56 026 469 (NIPPON DENKI K.K.) 14-03-1981, & JP56026469 A 00000000
		[X] - PATENT ABSTRACTS OF JAPAN, vol. 8, no. 63 (E-233)[1500], 24th March 1984; & JP-A-58 212 178 (MATSUSHITA DENKI SANGYO K.K.) 09-12-1983, & JP58212178 A 00000000

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