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EP0194916
European procedure
Extract from the Register of European Patents
EP About this file: EP0194916
| EP0194916 - Method of making integrated circuits by the MOS and CMOS technique, and CMOS structure [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 27.03.1990 Database last updated on 13.09.2024 | Most recent event Tooltip | 27.03.1990 | No opposition filed within time limit | published on 16.05.1990 [1990/20] | Applicant(s) | For all designated states STMicroelectronics S.A. 7, Avenue Galliéni 94250 Gentilly / FR | [N/P] |
| Former [1989/16] | For all designated states SGS-THOMSON MICROELECTRONICS S.A. 7, Avenue Galliéni F-94250 Gentilly / FR | ||
| Former [1989/09] | For all designated states SGS-THOMSON MICROELECTRONICS S.A. 101 Boulevard Murat F-75016 Paris / FR | ||
| Former [1989/02] | For all designated states THOMSON SEMICONDUCTEURS 101, bld Murat F-75016 - Paris / FR | ||
| Former [1986/38] | For all designated states SOCIETE POUR L'ETUDE ET LA FABRICATION DE CIRCUITS INTEGRES SPECIAUX - E.F.C.I.S. 17, avenue des Martyrs F-38100 Grenoble / FR | Inventor(s) | 01 /
Monroy, Agustin THOMSON-CSF SCPI 19, avenue de Messine F-75008 Paris / FR | 02 /
Prudhomme, Danielle THOMSON-CSF SCPI 19, avenue de Messine F-75008 Paris / FR | 03 /
Marty, Michel THOMSON-CSF SCPI 19, avenue de Messine F-75008 Paris / FR | [1986/38] | Representative(s) | Santarelli Tour Trinity 1 bis Esplanade de la Défense 92035 Paris La Défense Cedex / FR | [N/P] |
| Former [1989/03] | Rinuy, Santarelli 14, avenue de la Grande Armée F-75017 Paris / FR | ||
| Former [1988/33] | Rinuy, Santarelli 14, avenue de la Grande Armée F-75017 Paris / FR | ||
| Former [1986/38] | Guérin, Michel THOMSON-CSF SCPI B.P. 329 50, rue Jean-Pierre Timbaud F-92402 Courbevoie Cédex / FR | Application number, filing date | 86400403.1 | 25.02.1986 | [1986/38] | Priority number, date | FR19850002769 | 26.02.1985 Original published format: FR 8502769 | [1986/38] | Filing language | FR | Procedural language | FR | Publication | Type: | A1 Application with search report | No.: | EP0194916 | Date: | 17.09.1986 | Language: | FR | [1986/38] | Type: | B1 Patent specification | No.: | EP0194916 | Date: | 17.05.1989 | Language: | FR | [1989/20] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 09.07.1986 | Classification | IPC: | H01L21/265, H01L21/28, H01L21/82 | [1986/38] | CPC: |
H01L21/823814 (EP);
H01L21/28518 (EP)
| Designated contracting states | AT, CH, DE, FR, GB, IT, LI, NL [1986/38] | Title | German: | Verfahren zum Herstellen von integrierten Schaltungen durch MOS- und CMOS-Technologie und entsprechende CMOS-Struktur | [1986/38] | English: | Method of making integrated circuits by the MOS and CMOS technique, and CMOS structure | [1986/38] | French: | Procédé de fabrication de circuits intégrés en technologie MOS et CMOS, et structure CMOS correspondante | [1986/38] | Examination procedure | 08.10.1986 | Examination requested [1986/49] | 06.08.1987 | Despatch of a communication from the examining division (Time limit: M06) | 09.02.1988 | Reply to a communication from the examining division | 13.04.1988 | Despatch of communication of intention to grant (Approval: Yes) | 21.07.1988 | Communication of intention to grant the patent | 01.10.1988 | Fee for grant paid | 01.10.1988 | Fee for publishing/printing paid | Opposition(s) | 20.02.1990 | No opposition filed within time limit [1990/20] | Fees paid | Renewal fee | 18.01.1988 | Renewal fee patent year 03 | 18.02.1989 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]US4280271 (LOU PERRY W, et al); | [A]US4295897 (TUBBS GRAHAM S, et al); | [A]EP0072522 (SIEMENS AG [DE]); | [A]EP0135163 (SIEMENS AG [DE]); | [A]EP0139371 (TEKTRONIX INC [US]); | [Y]EP0054259 | [A] - IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. ED-30, no. 2, février 1983, pages 110-118, IEEE, New York, US; M. SUGINO et al.: "Latchup-free schottky-barrier CMOS" | Examination | EP0101000 |