EP0250869 - Semiconductor integrated circuit containing analogous and digital components [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 18.03.1993 Database last updated on 09.09.2024 | Most recent event Tooltip | 18.03.1993 | No opposition filed within time limit | published on 05.05.1993 [1993/18] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho, Saiwai-ku Kawasaki-shi Kanagawa-ken 210-0913 / JP | [N/P] |
Former [1988/01] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210 / JP | Inventor(s) | 01 /
Taguchi, Minoru c/o Patent Division Kabushiki Kaisha Toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | [1988/01] | Representative(s) | Lehn, Werner, et al Hoffmann Eitle, Patent- und Rechtsanwälte, Postfach 81 04 20 81904 München / DE | [N/P] |
Former [1988/01] | Lehn, Werner, Dipl.-Ing., et al Hoffmann, Eitle & Partner, Patentanwälte, Postfach 81 04 20 D-81904 München / DE | Application number, filing date | 87107683.2 | 26.05.1987 | [1988/01] | Priority number, date | JP19860121617 | 27.05.1986 Original published format: JP 12161786 | [1988/01] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0250869 | Date: | 07.01.1988 | Language: | EN | [1988/01] | Type: | B1 Patent specification | No.: | EP0250869 | Date: | 13.05.1992 | Language: | EN | [1992/20] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 08.10.1987 | Classification | IPC: | H01L21/76, H01L21/82 | [1988/01] | CPC: |
H01L21/76237 (EP,US);
H01L21/763 (EP,US);
H01L21/8226 (EP,US);
H01L21/8248 (EP,US);
H01L21/8249 (EP,US);
H01L27/0623 (EP,US);
H01L27/0203 (EP,US)
(-)
| Designated contracting states | DE, FR, GB [1988/01] | Title | German: | Integrierter Halbleiterschaltkreis mit analogen und digitalen Komponenten | [1988/01] | English: | Semiconductor integrated circuit containing analogous and digital components | [1988/01] | French: | Circuit intégré semi-conducteur comportant des composants analogiques et numériques | [1988/01] | Examination procedure | 26.05.1987 | Examination requested [1988/01] | 27.09.1989 | Despatch of a communication from the examining division (Time limit: M06) | 28.03.1990 | Reply to a communication from the examining division | 18.07.1990 | Despatch of a communication from the examining division (Time limit: M06) | 21.01.1991 | Reply to a communication from the examining division | 17.07.1991 | Despatch of communication of intention to grant (Approval: Yes) | 18.11.1991 | Communication of intention to grant the patent | 07.02.1992 | Fee for grant paid | 07.02.1992 | Fee for publishing/printing paid | Opposition(s) | 16.02.1993 | No opposition filed within time limit [1993/18] | Fees paid | Renewal fee | 16.05.1989 | Renewal fee patent year 03 | 16.05.1990 | Renewal fee patent year 04 | 17.12.1990 | Renewal fee patent year 05 |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]JP6057950 ; | [A]EP0013508 (FUJITSU LTD [JP]); | [X]EP0029987 (TOKYO SHIBAURA ELECTRIC CO [JP]); | [X]US4536945 (GRAY BRUCE [US], et al) | [A] - PATENT ABSTRACTS OF JAPAN, vol. 9, no. 189 (E-333)[1912], 6th August 1985; & JP-A-60 57 950 (HITACHI SEISAKUSHO K.K.) 03-04-1985, & JP6057950 A 00000000 | [A] - JAPANESE JOURNAL OF APPLIED PHYSICS, supplements 17th Conference on Solid State Devices and Materials, 25th-27th August 1985, pages 377-380, Tokyo, JP; M. SUZUKI et al.: "A 165ps/gate 5000-Gate ECL gate array" |