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EP0262531
European procedure
Extract from the Register of European Patents
EP About this file: EP0262531
| EP0262531 - Semiconductor memory device having data bus reset circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 25.02.1993 Database last updated on 06.07.2024 | Most recent event Tooltip | 25.02.1993 | No opposition filed within time limit | published on 14.04.1993 [1993/15] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | For all designated states FUJITSU VLSI LIMITED 1844-2, Kozoji-cho 2-chome Kasugai-shi Aichi 487 / JP | [N/P] |
| Former [1988/14] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | ||
| For all designated states FUJITSU VLSI LIMITED 1844-2, Kozoji-cho 2-chome Kasugai-shi Aichi 487 / JP | Inventor(s) | 01 /
Nakano, Masao Chuodaidanchi 228-911 1-3-2, Chuodai Kasugai-shi Aichi, 487 / JP | 02 /
Ohira, Tsuyoshi Fudogaoka-haitsu 102 926, Shimosakunobe Takatsu-ku Kawasaki-shi Kanagawa, 211 / JP | 03 /
Mochizuki, Hirohiko 2393-1-401, Arima Miyamae-ku Kawasaki-shi Kanagawa, 213 / JP | 04 /
Kodama, Yukinori Mezon-kikuna 301 7-3-38, Kikuna Kohoku-ku Yokohama-shi Kanagawa, 222 / JP | 05 /
Nomura, Hidenori Fujitsu-dai-1-eda-ryo 466-18, Edacho Midori-ku Yokohama-shi Kanagawa, 227 / JP | [1988/14] | Representative(s) | Schmidt-Evers, Jürgen, et al Mitscherlich PartmbB Patent- und Rechtsanwälte Postfach 33 06 09 80066 München / DE | [N/P] |
| Former [1988/14] | Schmidt-Evers, Jürgen, Dipl.-Ing., et al Patentanwälte Mitscherlich & Partner Postfach 33 06 09 D-80066 München / DE | Application number, filing date | 87113714.7 | 18.09.1987 | [1988/14] | Priority number, date | JP19860221019 | 19.09.1986 Original published format: JP 22101986 | [1988/14] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0262531 | Date: | 06.04.1988 | Language: | EN | [1988/14] | Type: | A3 Search report | No.: | EP0262531 | Date: | 04.07.1990 | Language: | EN | [1990/27] | Type: | B1 Patent specification | No.: | EP0262531 | Date: | 22.04.1992 | Language: | EN | [1992/17] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 14.05.1990 | Classification | IPC: | G11C7/00, G11C5/06, G11C11/24 | [1990/27] | CPC: |
G11C11/40 (KR);
G11C7/1048 (EP,US);
G11C7/20 (EP,US)
|
| Former IPC [1988/14] | G11C11/24, G11C7/00 | Designated contracting states | DE, FR, GB [1988/14] | Title | German: | Halbleiterspeicheranordnung mit einer Datenbus-Rücksetzungsschaltung | [1988/14] | English: | Semiconductor memory device having data bus reset circuit | [1988/14] | French: | Dispositif de mémoire à semi-conducteurs avec un circuit de remise de bus de données | [1988/14] | Examination procedure | 12.09.1990 | Examination requested [1990/45] | 26.08.1991 | Despatch of communication of intention to grant (Approval: Yes) | 23.10.1991 | Communication of intention to grant the patent | 10.12.1991 | Fee for grant paid | 10.12.1991 | Fee for publishing/printing paid | Opposition(s) | 23.01.1993 | No opposition filed within time limit [1993/15] | Fees paid | Renewal fee | 30.09.1989 | Renewal fee patent year 03 | 28.09.1990 | Renewal fee patent year 04 | 30.09.1991 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]JP57117181 ; | [A]JP59207086 ; | [A]GB2092403 (HITACHI LTD, et al) | [A] - PATENT ABSTRACTS OF JAPAN, vol. 6, no. 212 (P-151)[1090], 26th October 1982; & JP-A-57 117 181 (HITACHI) 21-07-1982, & JP57117181 A 00000000 | [A] - PATENT ABSTRACTS OF JAPAN, vol. 9, no. 76 (P-346), 5th April 1985; & JP-A-59 207 086 (FUJI XEROX) 24-11-1984, & JP59207086 A 00000000 |